IC Wafer Identification Features for Post-Dicing Traceability
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Solution Overview
Problem
Conventional integrated circuit (IC) wafer testing methods fail to accurately associate functional failures of individual circuit dies with their original location on the wafer, limiting quality management and traceability after dicing, as they only evaluate the entire wafer before dicing or individual units after manufacture without considering post-deployment characteristics.
Innovation Solution
Incorporating reference and identification features in multiple layers of each circuit die, with distinct offset vectors, to enable identification of the original location of each die after dicing, allowing for tracing back functional failures to their origin on the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional wafer testing methods are used to evaluate the entire wafer before dicing, then testing efficiency is maintained, but the ability to trace functional failures to specific die locations is lost
Solution Approach 1:
The patent divides the wafer into individually identifiable segments by embedding unique identification features in each die. These features include die location identifiers and batch identifiers that segment the continuous wafer into discrete, traceable units, enabling failure tracing to specific locations without requiring complex post-dicing analysis
Solution Approach 2:
The patent performs preliminary embedding of identification features during the wafer fabrication process itself, before dicing occurs. This preliminary action incorporates traceability information directly into the wafer structure, eliminating the need for complex post-dicing traceability systems and enabling straightforward failure location identification
2Reliability
If identification features are embedded in each circuit die, then traceability of individual dies is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the identification feature embedding process with the existing wafer fabrication process. The identification features are formed using the same photolithography and deposition techniques already employed for creating circuit patterns, combining multiple functions into a single integrated manufacturing flow without requiring separate manufacturing steps
Solution Approach 2:
The identification features serve multiple functions: they provide die location identification, batch identification, and enable both pre-dicing and post-dicing traceability. This multi-functionality reduces the need for separate identification systems and simplifies the overall manufacturing process while enhancing quality management capabilities
3Measurement precision
If reference features are positioned equidistant from scribe lines, then identification accuracy is improved, but the kerf region material loss increases
Solution Approach 1:
The patent uses partial identification features that are positioned within the functional die area rather than extending to the edges near scribe lines. This partial action approach provides sufficient identification accuracy for traceability while minimizing the impact on kerf region material, as the features are strategically placed to achieve the necessary precision without excessive material consumption
Data Source
AI summary
Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.