Multi-Voltage Integrated Circuit Well Biasing for Power Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices integrate more elements to perform complex operations, they consume increasing amounts of power, particularly due to the need for multiple supply voltages, leading to larger device sizes and higher power consumption.

Innovation Solution

The design of an integrated circuit (IC) with a multi-voltage circuit that includes a first and second well, each biased to different voltages, allowing for efficient signal shifting between voltage logic levels, reducing the area and power consumption by optimizing the layout and placement of transistors within the IC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple supply voltages are used to drive different elements, then functional complexity and operation capability are improved, but power consumption and device area increase

Engineering Contradiction:
Improveoperation capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The device is divided into multiple blocks, each block containing elements that operate at the same supply voltage. This segmentation allows independent power management for each block, enabling power consumption reduction by cutting off supply voltage to unused blocks while maintaining the ability to support multiple voltage levels for different functional requirements.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple supply voltages are used to drive different elements, then functional complexity and operation capability are improved, but device area increases

Engineering Contradiction:
Improveoperation capabilityVSAvoiddevice area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The device is divided into multiple blocks, each block containing elements that operate at the same supply voltage. This segmentation allows independent power management for each block, enabling area optimization by activating only the blocks needed for current operations while maintaining the ability to support multiple voltage levels for different functional requirements.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If transistors are disposed in multiple wells with different voltages, then signal shifting between voltage logic levels is enabled, but circuit complexity increases

Engineering Contradiction:
Improvevoltage level shifting capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple wells with different voltage biases are merged into a single integrated circuit block, allowing transistors to be selectively disposed in different wells based on the required voltage logic level. This merging enables voltage level shifting capability while managing complexity through unified block-level integration and systematic well arrangement.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9831877B2Integrated circuit and semiconductor device including the same
Publication Date: 2017.11.28 SAMSUNG ELECTRONICS CO LTD
  • US9831877B2 patent drawing
  • US9831877B2 patent drawing
  • US9831877B2 patent drawing

AI summary

An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.