IC Well Diode Protection Against Plasma-Induced Gate Damage
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Solution Overview
Problem
The miniaturization of integrated circuit (IC) devices has increased their susceptibility to damage due to factors like thinner gate dielectric thicknesses and the antenna effect, leading to plasma-induced gate oxide damage (PID) issues that affect yield and reliability during manufacturing.
Innovation Solution
Incorporation of a PID protection circuit comprising a pair of forward and reverse diodes electrically coupled in series between a doped well and the substrate to discharge accumulated electric charges, mitigating well-PID issues and ensuring the circuit can withstand high working voltages without affecting chip area or functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If miniaturization is pursued to reduce power consumption and increase functionality, then device performance is improved, but susceptibility to damage from antenna effect and plasma-induced gate oxide damage increases
Solution Approach 1:
The patent applies preliminary action by forming a protective structure (such as a pinned diode or protection circuit) in advance during the manufacturing process, before the device is operational. This protective structure is pre-configured to discharge accumulated electric charges from the antenna effect, preventing plasma-induced gate oxide damage before it can occur during subsequent manufacturing steps or device operation.
2Reliability
If protective structures are added to mitigate antenna effect, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the protective function with existing device structures by integrating the protection circuit or pinned diode into the existing circuit layout and manufacturing process. The protective structure shares common elements with the main circuit, such as using the same substrate, doping processes, and interconnect layers, thereby adding protection functionality without proportionally increasing overall device complexity.
Solution Approach 2:
The protective structure is designed to serve multiple functions: it protects against plasma-induced gate oxide damage from the antenna effect, provides electrostatic discharge protection, and can function as part of the normal circuit operation. This multi-functionality reduces the need for separate dedicated protection components, thereby limiting the increase in device complexity.
3Object-affected harmful factors
If protective circuits are implemented to discharge electric charges, then damage resistance is improved, but manufacturing process complexity increases
Solution Approach 1:
The protective structure is formed during early manufacturing stages using standard semiconductor fabrication processes such as doping, oxidation, and deposition. By establishing the protective structure in advance, the patent ensures that charge discharge capability is built into the device before subsequent manufacturing steps that might generate antenna effect charges, simplifying the overall manufacturing flow compared to adding protection layers after device assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents or mitigates PID damage by discharging electric charges before they reach the gate dielectric, ensuring reliable operation and compatibility with various technology nodes and voltage applications.
Implementation Method 1
a pair of PID protection devices correspondingly configured as a forward diode and a reverse diode electrically coupled in series between a doped well and a substrate... configured to discharge electric charges accumulated in the doped well to the substrate
Data Source
AI summary
An integrated circuit (IC) device includes a substrate, first and second semiconductor devices correspondingly in different first and second doped regions in the substrate. A gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The IC device further includes a first reverse diode electrically coupled between the substrate and a doped well. The doped well is in the first doped region and a source/drain of the first semiconductor device is in the doped well. Alternatively, the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.