IC Wire Rasterization for Fast Parasitic Extraction
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Solution Overview
Problem
Existing techniques struggle to accurately model parasitic capacitance, resistance, and inductance in semiconductor designs, especially at smaller process geometries, due to increasing manufacturing process variations and complex geometries, impacting circuit delay, energy consumption, and reliability.
Innovation Solution
A method using neural networks to rasterize wire structures into pixel-based definitions, generating parasitic parameters by training on curvilinear and rectilinear shapes, and incorporating manufacturing process information to predict parasitic effects, leveraging GPU and TPU architectures for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional parasitic extraction techniques are used, then manufacturing process variations and complex geometries at smaller process geometries make accurate modeling difficult, but the existing techniques are relatively slow in computing parasitic parameters
Solution Approach 1:
The patent replaces traditional field solver computational methods with a neural network-based system. The neural network is trained on parasitic parameters extracted by field solvers, then uses this learned knowledge to rapidly predict parasitic parameters without requiring repeated field solver computations, thus substituting a slower mechanical/computational process with a faster intelligent system.
Solution Approach 2:
The patent performs preliminary training of the neural network using field solver data before actual parasitic extraction. This preliminary action creates a pre-trained model that can quickly predict parasitic parameters for new designs without requiring time-consuming field solver runs, enabling fast computation while maintaining accuracy.
2Reliability
If manufacturing process variations increase at smaller geometries, then parasitic modeling accuracy deteriorates, but the complexity of modeling and extraction increases
Solution Approach 1:
The patent incorporates manufacturing process information as additional inputs to the neural network, allowing the model to adapt to different process variations. By training the neural network on data from multiple process corners and variations, the system learns to predict parasitic parameters accurately under different manufacturing conditions without increasing modeling complexity for the user.
Solution Approach 2:
The patent introduces a neural network as an intermediary between the complex physical processes of parasitic generation and the final parameter extraction. This intermediary learns the complex relationships between geometry, process variations, and parasitic parameters, simplifying the overall modeling process while improving accuracy across different manufacturing conditions.
Data Source
AI summary
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.