IC Wiring Structure With Air Gaps for Lower Capacitance
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Solution Overview
Problem
As integrated circuits are miniaturized, the wiring structures face challenges with increased resistance and leakage current, necessitating improvements in performance and reliability.
Innovation Solution
The integration of a specific wiring structure design involving etch stop layers and inter-wiring insulating films that create voids between wiring patterns, reducing parasitic capacitance and electromigration through controlled etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If wiring structures are miniaturized to improve integration density, then device integration is enhanced, but resistance and leakage current of the wiring structure increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform wiring structure where the upper pattern has a greater width than the lower pattern. This local variation in cross-sectional area compensates for the miniaturization effects, maintaining lower resistance and leakage current in the critical upper region while preserving overall device integration density.
Solution Approach 2:
The patent transitions from a two-dimensional planar wiring view to a three-dimensional structure by forming patterns with different widths at different heights. The upper pattern extends further laterally than the lower pattern, utilizing the vertical dimension to increase effective conduction area without increasing the device footprint.
2Reliability
If etch stop layers and inter-wiring insulating films are integrated to create voids between wiring patterns, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent segments the inter-wiring insulating film into multiple portions separated by etch stop layers. This segmentation creates distinct regions including voids between wiring patterns, allowing independent control of electrical properties in different zones while managing parasitic capacitance through spatial separation.
Solution Approach 2:
The patent introduces voids (air gaps) as porous regions within the inter-wiring insulating structure. These voids have lower dielectric constants than solid insulating materials, thereby reducing parasitic capacitance between adjacent wiring patterns while maintaining the necessary insulating function.
Data Source
AI summary
According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.