Integrated Circuit Wiring Insulation Structure for Leakage Current Reduction
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Solution Overview
Problem
Integrated circuit devices face challenges with leakage current and time-dependent dielectric breakdown (TDDB) due to the miniaturization of multi-layer wiring structures, and the risk of short circuits from misalignment during the manufacturing process, which affects electrical characteristics and reliability.
Innovation Solution
The integrated circuit device incorporates a specific structure with a first insulation layer, a lower wiring structure, an etch stop layer, a capping layer, and an upper wiring structure, including a concave-convex structure to prevent leakage current and misalignment-induced short circuits, using materials like aluminum oxide and carbon-containing layers to enhance process margins and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the line width and pitch of multi-layer wiring structure are reduced to enable miniaturization, then the integration density increases, but leakage current increases and TDDB reliability deteriorates
Solution Approach 1:
The patent segments the insulation layer into multiple portions: a first insulation layer portion filling the groove, a second insulation layer portion on the etch stop layer, and a third insulation layer portion in the concave region. This segmentation allows different insulation regions to be optimized independently, with thicker effective insulation at critical leakage paths while maintaining overall miniaturization
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a groove structure and filling it with insulation material, then adding a concave-convex structure on top. This transforms the 2D plane reduction problem into a 3D vertical stacking problem, achieving miniaturization in the plane while compensating leakage current through vertical insulation enhancement
2Ease of manufacture
If the process margin is insufficient during upper wiring structure formation, then manufacturing complexity decreases, but misalignment occurs causing short circuits
Solution Approach 1:
The etch stop layer is formed preliminarily before the upper wiring structure, creating a reference plane and physical barrier that prevents misalignment. The concave-convex structure is also formed in advance to guide the upper wiring positioning, ensuring proper alignment even with reduced process margins
Solution Approach 2:
The etch stop layer acts as an intermediary between the lower wiring structure and the upper wiring structure. It provides a stable reference surface for etching the upper wiring groove and prevents direct contact between adjacent wiring structures, serving as a mediator that eliminates short circuits from misalignment
3Device complexity
If a conventional flat insulation structure is used, then device complexity is low, but leakage current occurs at the wiring interface
Solution Approach 1:
The patent applies local quality by creating a concave region specifically at the location where the upper wiring structure contacts the lower wiring structure. The third insulation layer portion is placed only in this critical concave region, providing enhanced local insulation exactly where leakage current is most likely to occur, rather than uniformly increasing insulation everywhere
Data Source
AI summary
An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.