Integrated Circuit Wiring Recess Formation via Segmented Mask Etching
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Solution Overview
Problem
The challenge in manufacturing integrated circuit devices is the reduced process margin for interconnecting wiring layers and via plugs due to down-scaling, which affects the reliability and efficiency of the manufacturing process.
Innovation Solution
A method involving the sequential formation of device layers, wiring insulating layers, and hard mask layers on a semiconductor substrate, where specific mask layers and etch masks are used to create recesses and stitch regions, allowing for the formation of wiring structures that are electrically connected to semiconductor devices, even with reduced process margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If down-scaling of integrated circuit devices is advanced, then device integration and miniaturization are improved, but process margin for interconnecting wiring layer and via plug is reduced
Solution Approach 1:
The patent divides the via plug formation process into multiple stages: forming recesses at different depths in different regions, selectively removing etch stop films in specific areas, and creating wiring recesses at different levels. This segmentation allows precise control of each via plug's depth and position, maintaining manufacturing precision despite device down-scaling.
Solution Approach 2:
The patent performs preliminary actions by forming an etch stop film before via plug formation, creating recesses at predetermined depths, and selectively removing portions of the etch stop film in advance. These preliminary actions establish precise depth control and positioning for subsequent wiring formation, ensuring adequate process margin even at smaller device dimensions.
2Manufacturing precision
If multiple etch masks and mask layers are used to form recesses and stitch regions, then wiring structure precision is improved, but device complexity increases
Solution Approach 1:
The patent uses multiple mask layers (first mask layer, second mask layer, third mask layer) and etch masks sequentially to divide the via plug formation into distinct stages. Each mask layer defines specific regions for recess formation or etch stop film removal, enabling precise control of wiring structure geometry while managing process complexity through systematic segmentation.
Solution Approach 2:
The patent applies different processing conditions to different regions: removing etch stop films in first regions but not in second regions, forming recesses to different depths in different areas, and selectively creating wiring recesses. This local quality approach ensures precise wiring structure formation by tailoring each region's processing to its specific requirements.
Data Source
AI summary
Methods of manufacturing an integrated circuit device are provided. A method of manufacturing an integrated circuit device includes sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening and a second mask layer having a second opening as an etch mask, respectively. The method includes forming a first wiring recess through the wiring insulating layer and a second wiring recess having a depth that is less than that of the first wiring recess by removing a portion of the wiring insulation layer by using a portion of the hard mask layer as an etching mask. Moreover, the method includes forming a wiring structure that is in the first wiring recess and the second wiring recess.