IC Yield Estimation via Geometric Failure Regions
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Solution Overview
Problem
Existing design verification tools assume monotonic failure along a single vector of input space when evaluating integrated circuit designs, which breaks down when multiple combinations of manufacturing parameters cause failures, making it difficult to accurately estimate yield for rare failure events.
Innovation Solution
A computing system implements a circuit verification tool that performs scaled sampling of parameter values in foundry models, simulates the circuit design with these samples, builds a geometric model to describe failure regions, and estimates yield based on these regions, allowing for a more comprehensive analysis of manufacturing variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Monte Carlo sampling is performed with selection of samples farthest from nominal parameter value and simulation at PVT corners, then designers can be informed about rare failure occurrences for single parameter combinations, but the assumption of monotonic failure along single vector breaks down when multiple different combinations of variable manufacturing parameters correspond to failures
Solution Approach 1:
The patent transitions from analyzing failures along a single monotonic vector to mapping failures in a multi-dimensional parameter space. By selecting multiple PVT corners that represent different extremes of process, voltage, and temperature variations, the method captures failure modes that occur at different corners, thereby accounting for multiple combinations of manufacturing parameters rather than assuming a single failure vector.
Solution Approach 2:
The patent systematically varies multiple parameters simultaneously (process corner, voltage corner, temperature corner) rather than changing a single parameter. This multi-parameter variation approach allows the detection of failures caused by different combinations of parameter deviations from nominal values, resolving the limitation of single-vector monotonic failure assumptions.
2Adaptability or versatility
If design verification tool evaluates circuit design against foundry models with multiple variable parameters, then comprehensive manufacturing variability can be analyzed, but determining probability of failure becomes complex when multiple parameter combinations cause failures
Solution Approach 1:
The patent divides the continuous parameter space into discrete segments by selecting specific PVT corners. Instead of evaluating all possible parameter combinations, the method segments the variability space into representative corners (e.g., FF, FS, SF, SS for process; HV, LV for voltage; TC, TT for temperature) and evaluates failures at each segment independently, simplifying the overall failure probability calculation.
Solution Approach 2:
The patent creates simplified representations of the complex parameter space by using discrete PVT corners that copy the essential variability characteristics. Each corner represents a specific combination of parameter extremes, serving as a simplified model that captures the behavior of the full continuous parameter distribution without requiring exhaustive analysis of all possible combinations.
Data Source
AI summary
A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.