Inter-Component Communication Interface Pin Reduction
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Solution Overview
Problem
Current inter-component communication methods, such as the LPC bus, are inadequate for handling the demands of modern peripheral devices due to high pin requirements, low bandwidth, and outdated signaling technologies, making them inefficient for new generation peripheral devices that require low-cost and medium-bandwidth connections.
Innovation Solution
The implementation of an inter-component communication interface (ICCI) that uses a master and slave configuration with logic units, registers, clock, data, and chip select pins to enable efficient communication, allowing for slave-initiated transactions and supporting multiple channels for peripheral access, virtual wire messaging, and out-of-band messages, thereby reducing pin usage and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the LPC bus is used for peripheral communication, then pin efficiency is improved compared to ISA bus, but bandwidth remains low at 133 Mbps and requires at least 7 pins plus optional pins
Solution Approach 1:
The patent changes the signaling parameters by using differential signaling (SDA/SCL) instead of single-ended signaling, and implements variable clock speeds (100 kHz, 400 kHz, 1 MHz) to achieve higher bandwidth while maintaining pin efficiency. This allows the bus to scale performance without adding pins.
Solution Approach 2:
The patent implements dynamic clock stretching capability where the slave device can hold the clock signal low to extend the communication time, enabling flexible data transfer rates and handling of varying data preparation times without requiring additional control pins.
2Productivity
If high speed bus like PCI Express is used, then bandwidth is improved, but cost increases significantly
Solution Approach 1:
The patent achieves variable bandwidth performance through parameter changes in the existing 2-wire interface by adjusting clock speed (from 100 kHz to 1 MHz) and using clock stretching, providing medium bandwidth capability at low cost without requiring expensive high-speed bus infrastructure.
Solution Approach 2:
The patent makes the 2-wire interface multi-functional by supporting both traditional low-speed control applications and medium-speed data transfer through variable clocking and clock stretching, replacing the need for multiple specialized interfaces and reducing overall system cost.
3Productivity
If more pins are added to increase bandwidth, then productivity is improved, but device complexity and cost increase
Solution Approach 1:
The patent uses periodic clock cycling with variable frequencies (100 kHz, 400 kHz, 1 MHz) to achieve higher effective data transfer rates within the same 2-wire interface, scaling bandwidth through time-based multiplexing rather than adding parallel data pins.
Solution Approach 2:
The patent nests multiple communication modes (standard mode, fast mode, clock stretching mode) within a single 2-wire interface framework, allowing the system to select appropriate bandwidth levels without requiring additional physical pins for each mode.
Data Source
AI summary
Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.