Integrated Clock Gating Chain for Scan Test Power Reduction
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Solution Overview
Problem
The existing semiconductor integrated circuits experience high power consumption during scan tests due to all sequential circuits operating simultaneously with the clock signal, which is not efficiently managed by current clock gating technologies.
Innovation Solution
The implementation of an Integrated Clock Gating (ICG) chain with ICG circuits that supply circuit clock signals to scan chains with timing differences, achieved through an ICG enable propagation signal that propagates sequentially, allowing only one scan chain to operate at a time, thereby reducing simultaneous operations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all sequential circuits operate simultaneously with the clock signal during scan tests, then test execution is complete and thorough, but instantaneous power consumption becomes excessively high
Solution Approach 1:
The patent segments the scan chains into multiple groups, each group being supplied with the clock signal at different timings through separate ICG circuits. This segmentation allows the sequential circuits to be divided into multiple operational phases, preventing simultaneous operation of all circuits and thereby reducing instantaneous power consumption while maintaining complete test coverage across all segments
2Use of energy by stationary object
If clock gating technology is used to supply clock signals, then power consumption is suppressed during normal operation, but all sequential circuits still operate simultaneously during scan tests
Solution Approach 1:
The patent introduces dynamic timing control for clock signal supply to different scan chain groups during scan tests. By dynamically adjusting the clock signal timing for each ICG circuit based on the ICG enable propagation signal, the system transforms the static simultaneous operation into a dynamic sequential operation, maintaining power consumption suppression benefits while enabling complete test execution
Data Source
AI summary
A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.