ICG Hierarchy Verification for Clock Deadlock Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face issues with clock signal control, leading to unexpected operation and high power consumption due to potential clock deadlocks, which existing technologies fail to detect and address effectively.
Innovation Solution
A clock deadlock detecting system and method that extracts hierarchy information of integrated clock gating cells, generates checking properties using integrated circuit design information, and applies a formal method to determine whether cells are expected to fall into clock deadlock states, modifying the design information accordingly to prevent such deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are controlled to reduce power consumption, then power consumption is reduced, but the circuit may unexpectedly operate due to clock deadlocks
Solution Approach 1:
The patent applies preliminary action by performing formal verification checks on clock gating cell designs before actual circuit fabrication. The system extracts hierarchy information, generates checking properties, and verifies clock deadlock freedom in advance, preventing unreliable circuit behavior while maintaining power-saving clock control mechanisms.
Solution Approach 2:
The patent implements feedback by using formal verification to check clock deadlock properties and providing results that indicate whether the design is free from clock deadlocks. This feedback loop allows designers to identify and correct potential reliability issues before manufacturing, ensuring both power efficiency and operational reliability.
2Measurement precision
If formal verification is applied to detect clock deadlocks, then detection accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the verification process into distinct modular components: extracting hierarchy information from design data, generating checking properties based on ICG cell structures, and performing formal verification. This modular approach improves detection accuracy while managing computational complexity through structured processing.
Solution Approach 2:
The patent uses an intermediary approach by introducing a formal verification system that acts as a mediator between the circuit design and the detection process. The system translates design information into checking properties and uses formal methods to verify clock deadlock freedom, achieving high detection accuracy through a structured intermediate verification layer.
Data Source
AI summary
A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.