Integrated Clock Gate Activity Modeling for Vectorless Power Analysis
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Solution Overview
Problem
Conventional EDA tools use vectorless power analysis based on worst-case assumptions, leading to overly pessimistic power consumption assessments, which can result in unnecessary optimizations and inefficient resource usage due to the assumption that all integrated clock gaters are active, failing to provide a realistic behavioral picture of IC power consumption.
Innovation Solution
An EDA system that calculates slack values for integrated clock gaters through static timing analysis, generates a priority list, and selectively activates them during power analysis, propagates state stimuli, and calculates power consumption based on global activity, breaking the worst-case scenario assumption and providing a more realistic power consumption analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional EDA tools use vectorless power analysis assuming all integrated clock gaters are active, then power analysis can be performed without simulation, but the power consumption assessment becomes overly pessimistic and inaccurate
Solution Approach 1:
The patent changes the parameter of clock gater activity from the fixed worst-case assumption (all active) to a dynamic model based on slack values and user-defined priorities. This allows the power analysis to adapt to different operational scenarios, improving accuracy while maintaining computational efficiency.
Solution Approach 2:
The patent introduces dynamic selection of active clock gaters based on slack values and priority inputs rather than static worst-case assumptions. The system dynamically determines which clock gaters to activate during power analysis, enabling more realistic power consumption modeling without requiring full vector-based simulation.
2Loss of time
If conventional EDA tools assume all integrated clock gaters are turned on for power analysis, then the analysis is simple and fast, but it leads to unnecessary optimizations and inefficient resource usage
Solution Approach 1:
The patent changes the activity parameter of clock gaters from a fixed worst-case assumption to a dynamic model based on slack values and user priorities. This allows the system to identify which clock gaters are actually active under given conditions, avoiding unnecessary optimizations and improving resource utilization efficiency.
3Measurement precision
If the EDA tool selectively activates integrated clock gaters based on slack values and priorities, then power consumption assessment becomes more realistic, but the analysis complexity increases
Solution Approach 1:
The patent segments the clock gater network into active and inactive groups based on slack values and user-defined priorities. By dividing the analysis into manageable segments (selected clock gaters vs. non-selected ones), the system achieves more accurate power analysis without requiring complete simulation of the entire circuit, thus controlling complexity.
Solution Approach 2:
The patent applies partial action by analyzing only the subset of clock gaters that are selected based on slack values and priorities, rather than analyzing all clock gaters uniformly. This partial analysis approach provides sufficient accuracy for power consumption assessment while significantly reducing computational complexity compared to full vector-based simulation.
Data Source
AI summary
Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated during power analysis based on the priority list and the priority inputs from the user. The systems and methods may propagate a set of state stimuli through the output cones of the selected ICGs and calculate the current through and power consumed by circuit devices in the output cones based on the state propagation and global data activity.