ICN Router Hierarchical Cache Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Information Centric Networking (ICN) routers face limitations in scaling cache sizes to multi-Terabyte levels while maintaining multi-Gbps line-speed operations due to memory access latency and throughput constraints of existing memory technologies.
Innovation Solution
A multi-layer hierarchical caching system is introduced, utilizing a small but fast Dynamic Random Access Memory (DRAM) cache layer (L1) for immediate data retrieval and a large but slower Solid-State Drive (SSD) cache layer (L2) for storing a significant portion of the catalog, with proactive prefetching and batching techniques to overcome latency issues and achieve high transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large cache size is implemented using current memory technologies, then the cache capacity increases, but the memory access latency increases and throughput decreases
Solution Approach 1:
The cache memory is segmented into multiple banks (first cache bank and second cache bank) with different characteristics. The first cache bank uses high-speed memory for low-latency access, while the second cache bank uses high-capacity memory for large storage. This segmentation allows the system to achieve both large cache size and low access latency by directing requests to appropriate cache banks based on data type and access patterns.
2Quantity of substance
If a large cache size is implemented using current memory technologies, then the cache capacity increases, but the sustainable data rate decreases
Solution Approach 1:
The cache system is divided into parallel cache banks that can operate simultaneously. The first cache bank handles hot data with high throughput requirements, while the second cache bank stores cold data. This parallel segmentation enables the system to sustain high data rates by processing multiple cache operations concurrently across different banks.
Solution Approach 2:
The system performs preliminary actions by pre-fetching data into the first cache bank before it is actually needed. When data is accessed frequently, it is proactively loaded into the high-speed first cache bank from the second cache bank, ensuring that subsequent accesses can be served at high speed without waiting for slower memory operations.
3Loss of time
If high-speed memory is used for the cache, then the access latency decreases, but the cache capacity is limited to about 10GB
Solution Approach 1:
The cache is segmented into two distinct banks: the first cache bank uses high-speed memory technology to achieve low access latency, while the second cache bank uses high-capacity memory technology to provide large storage. This segmentation resolves the contradiction by allowing each bank to optimize for its specific function rather than requiring a single memory type to satisfy both requirements.
Solution Approach 2:
The first cache bank acts as an intermediary between the processor and the second cache bank. Frequently accessed data is kept in the first cache bank for rapid access, while less frequently accessed data resides in the second cache bank. This intermediary structure enables the system to achieve both low latency for hot data and high capacity for cold data.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present invention relates to an ICN router (1), comprising a first cache layer (L1) and a second cache layer (L2), the first cache layer (L1) comprising a first content memory (11) and the second cache layer (L2) comprising a second content memory (21), the second content memory (21) having a higher capacity but a slower access speed than the first content memory (11), the router (1) being configured so that the first cache layer (L1) is adapted to fetch data from second cache layer (L2) when the router (1) is requested to output said data, characterized in that the first content memory (11) presents a first block size and the second content memory (21) presents a second block size, the second block size being higher that the first block size, the first content memory (11) comprising a swap area (110) through which the first content memory (11) is connected to the second content memory (21), the swap area (110) being adapted for individually serving blocks at the first block size as parts of blocks at the second size fetched from the second content memory (21).