Inter-Domain Clock Controller for Multi-Clock-Domain IC Testing
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Solution Overview
Problem
Conventional test techniques are ineffective in screening timing-related defects in modern small-feature-size digital ICs, especially those operating at GHz frequencies, and existing methods for at-speed testing of multi-clock-domain ICs are inflexible and costly, requiring additional logic and increased area overhead.
Innovation Solution
The introduction of an 'inter-domain on-chip-clock controller' (icOCC) that synchronizes test clock signals from external ATE and internal generators across different clock domains, enabling deterministic control of clock signal phases for scan shift and capture steps, and allowing for efficient at-speed testing without modifying existing test protocols or architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test techniques (stuck-at-fault testing with IDDQ) are used, then testing simplicity is maintained, but timing-related defects in GHz-range multi-clock-domain ICs cannot be detected
Solution Approach 1:
The patent implements dynamic clock domain mapping that allows the test architecture to adaptively configure which clock domains are active during testing. The system can dynamically select and activate specific clock domains based on the test requirements, enabling effective detection of timing-related defects across GHz-range multi-clock-domain ICs while maintaining testing flexibility.
Solution Approach 2:
The patent changes the operational parameters of the test system by introducing at-speed testing capabilities that operate at the actual GHz-range frequencies of the target IC. This parameter change from conventional low-speed testing to high-speed at-speed testing enables detection of timing-related defects that conventional techniques cannot detect.
2Reliability
If additional logic is added to support intra-clock at-speed testing, then test coverage is improved, but area overhead increases
Solution Approach 1:
The patent implements a universal test architecture where a single clock domain mapping structure serves multiple purposes: it supports both inter-clock domain testing and intra-clock domain testing. This multi-functional design eliminates the need for separate additional logic structures, thereby improving test coverage without proportionally increasing area overhead.
Solution Approach 2:
The patent merges the clock domain mapping functionality with the existing scan chain infrastructure. By combining these functions into a unified structure rather than adding separate dedicated logic, the system achieves comprehensive test coverage while minimizing the additional area required for testing capabilities.
3Adaptability or versatility
If a single type of test-clock pair is generated, then clock control simplicity is maintained, but flexibility for efficient ATPG software techniques is reduced
Solution Approach 1:
The patent implements dynamic clock domain mapping that allows the test architecture to adaptively configure which clock domains are active during testing. The system can dynamically select and activate specific clock domains based on the test requirements, enabling effective detection of timing-related defects across GHz-range multi-clock-domain ICs while maintaining testing flexibility.
4Ease of manufacture
If on-chip clock sources (PLLs, digital dividers) are used for at-speed testing, then cost of ATE tool is reduced, but control over clock signal phases becomes less precise
Solution Approach 1:
The patent introduces an intermediary clock domain mapping structure that sits between the on-chip clock sources and the scan chains. This intermediary layer provides deterministic control over clock signal phases and frequencies by mapping clock domains in a controlled manner, thereby maintaining precision while using cost-effective on-chip clock sources instead of expensive external ATE tools.
Data Source
AI summary
An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.