ID-Based PCIe Endpoint Lending Routing
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Solution Overview
Problem
Existing PCIe device lending solutions face challenges in providing full access to the address space of both lender and lendee devices without requiring changes to the PCIe endpoints or remote lendee devices, leading to degraded system performance.
Innovation Solution
The implementation of ID-based transaction routing, where a lookup table at the host lending computer system maps incoming Requester ID (RID) values from PCIe endpoint devices to network-on-chip (NoC) target port number values, enabling sharing of PCIe endpoint functionality without altering the PCIe endpoints or remote lendee devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If address-based routing is used in PCIe device lending, then routing simplicity is maintained, but address space accessibility is limited
Solution Approach 1:
The patent introduces an intermediary translation mechanism between the address-based routing system and the endpoint device access requirements. The lender PCIe controller acts as an intermediary that receives address-based requests, translates them through the address map to identify the correct lendee device, and forwards the translated requests appropriately. This intermediary translation layer enables full address space accessibility while maintaining the simplicity of address-based routing for the host system.
2Adaptability or versatility
If data is moved in lendee space to make full lendee space accessible, then address space accessibility is improved, but system performance is degraded
Solution Approach 1:
The patent replaces the mechanical data movement approach with an intelligent routing substitution. Instead of physically moving data between address spaces through software intervention, the system substitutes the traditional address-based routing mechanism with an enhanced routing approach that uses address map translation. This substitution enables direct access to the full lendee address space through properly translated requests, eliminating the need for data movement and preserving system performance.
3Adaptability or versatility
If lender device configuration is adjusted to support device lending, then endpoint accessibility is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the routing parameters of the lender PCIe controller through configuration space registers. The address map is programmed as a configuration parameter that maps endpoint device addresses to lendee device addresses. This parameter-based configuration approach enables the lender device to support multiple lending scenarios without hardware redesign, maintaining device simplicity while improving endpoint accessibility through flexible parameter adjustment.
4Measurement precision
If custom header fields are added to PCIe TLP packets for device lending, then routing precision is improved, but compatibility is reduced
Solution Approach 1:
The patent achieves routing precision using existing universal PCIe transaction fields rather than custom header fields. The address map translation mechanism utilizes the standard PCIe address fields that are already present in TLP packets, making the solution compatible with all standard PCIe devices. The same translation mechanism works for different types of PCIe transactions (memory reads, writes, I/O operations) without requiring transaction-type-specific custom headers, thus maintaining universality and compatibility while achieving precise routing to the correct lendee devices.
Data Source
AI summary
A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.