Identifier Verification for Rapid Processing Unit Failure Detection
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Solution Overview
Problem
Conventional information processing devices lack a means to quickly detect failures in processing units that process multiple information pieces, leading to incorrect output and prioritization of processing rate over error correction, especially in digital signal processing where latency is critical.
Innovation Solution
An information processing device with an identifier assignment unit, input and output memories, and an identifier verification unit that assigns and verifies identifiers for each information piece to determine if the processed information is correctly outputted, allowing for rapid detection of processing unit failures and subsequent error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processing unit processes multiple information pieces at high speed, then processing rate is improved, but detection of processing errors becomes delayed
Solution Approach 1:
The patent applies preliminary action by assigning identifiers to information pieces before processing occurs. This pre-assignment of unique identifiers to each information piece (e.g., each channel's data) enables subsequent rapid verification without adding processing delay. The identifier is attached in advance so that when verification is needed, it can be immediately checked against the output, thus maintaining high processing rates while enabling fast error detection.
Solution Approach 2:
The patent implements feedback by creating a verification mechanism that compares identifiers from input memories with identifiers from output memories. This feedback loop continuously monitors whether processed information has been correctly routed to the appropriate output memory. When a mismatch is detected, it indicates a processing error, allowing for immediate detection without compromising the high-speed processing of multiple information pieces.
2Reliability
If identifier verification is performed for all output memories, then error detection reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by maintaining identifier copies in both input memories and output memories. Instead of complex verification logic, the system simply copies the identifier assignment information to the output memory alongside the processed data. The verification process then becomes a simple comparison of these copied identifiers, significantly reducing system complexity while maintaining high reliability in error detection.
Solution Approach 2:
The patent applies universality by using a single identifier assignment mechanism that serves multiple purposes: it labels information pieces for tracking, enables error detection through verification, and provides a basis for identifying the nature of errors. This multi-functional use of identifiers simplifies the overall system architecture, as one mechanism accomplishes what would otherwise require multiple separate systems.
Data Source
AI summary
Failure of a processing unit that processes a plurality of information pieces is discovered in a short time. An information processing device 100 including a processing unit 1 that processes a plurality of information pieces includes: an identifier assignment unit 2 that assigns identifiers 60000 to 61023 to the plurality of information pieces 40000 to 41023, respectively; a plurality of input memories 20000 to 21023 that retain the plurality of information pieces 40000 to 41023 and the identifiers 60000 to 61023 assigned to the plurality of information pieces 40000 to 41023, respectively; a plurality of output memories 30000 to 31023 that retain the plurality of information pieces 50000 to 51023 processed by the processing unit 1 and the identifiers 70000 to 71023 assigned to the plurality of processed information pieces 50000 to 51023, respectively; an identifier verification unit 3 that verifies the identifiers 70000 to 71023 by comparing the identifiers 70000 to 71023 with the identifiers 60000 to 61023, respectively; and an error handling unit 4 that performs error handling when identifiers do not match with each other.