Idle Aggregation Unit for IC Power Optimization
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Solution Overview
Problem
Integrated circuits face challenges in effectively managing power consumption, particularly in systems that operate on battery power, as existing methods like clock gating and power gating do not fully optimize dynamic power savings by not considering the idleness of all functional units simultaneously.
Innovation Solution
A system and method that includes an idle aggregation unit to coordinate the idleness of multiple functional units, asserting idle requests and acknowledgments to gate the clock signal only when all units are idle, preventing unnecessary power consumption and allowing for dynamic power savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is applied to individual functional units independently, then dynamic power savings are achieved in those units, but overall power optimization is suboptimal because idle aggregation across all units is not considered
Solution Approach 1:
The patent merges the idle detection and clock gating control of multiple functional units into a single unified idle aggregation unit. This unit aggregates idle signals from all functional units and generates a single clock gating control signal when all units are idle, thereby achieving system-wide power optimization without requiring complex independent control logic for each unit.
Solution Approach 2:
The idle aggregation unit acts as an intermediary between individual functional units and the clock gating mechanism. It receives idle indications from functional units, processes the aggregated idle status, and controls the clock signal distribution accordingly, simplifying the overall control architecture while enabling coordinated power management.
2Use of energy by moving object
If power gating is applied to a gated power domain, then additional power savings are achieved, but the system cannot respond quickly enough when individual functional units become active again
Solution Approach 1:
The patent segments the power management approach by applying clock gating at the functional unit level rather than gating entire power domains. This allows individual functional units to be independently controlled - clock signals can be gated to specific idle units while keeping other units active, enabling faster response when any unit becomes active without the latency of power domain wake-up sequences.
3Loss of energy
If clock signals are gated to idle synchronous circuitry, then dynamic power consumption is reduced, but system-wide coordination of idle states is lost
Solution Approach 1:
The idle aggregation unit implements feedback by continuously monitoring idle indication signals from all functional units and adjusting the clock gating control accordingly. When any functional unit transitions from idle to active state, its idle indication changes, triggering the idle aggregation unit to remove clock gating from all units, ensuring system-wide coordination of idle states while maintaining dynamic power savings.
Data Source
AI summary
A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.