Memory Chip Bus Wiring with Idle Lines for Crosstalk and Voltage Drop
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Solution Overview
Problem
The existing wiring configurations in memory chips, such as DRAM, face issues with cross-talk between neighboring wires and voltage drops/glitches in power supply wires due to parasitic couplings, which affect data transmission speed and power integrity, and are challenging to address without increasing production costs or chip area.
Innovation Solution
The solution involves reconfiguring data bus wires and power supply wires by utilizing non-active signal wires as additional power supply wires and implementing a control circuit to form electrical paths that reduce effective resistance and inductance, thereby minimizing cross-talk and voltage drops, and using static signals to provide shielding effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If data bus wires and power supply wires share the same metal layer, then chip area is reduced and production cost is lowered, but cross-talk between neighboring wires and voltage drops occur due to parasitic couplings
Solution Approach 1:
The patent segments the power supply network by introducing separate power supply metal layers (first and second power supply metal layers) distinct from the signal transmission metal layers. This segmentation allows power wires and data bus wires to be physically separated in different metal layers, eliminating parasitic couplings while maintaining compact chip area through vertical stacking of functional layers.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout where power and signal wires share the same metal layer to a three-dimensional multi-layer architecture. By utilizing vertical stacking with dedicated power supply metal layers and signal transmission metal layers, the patent achieves spatial separation of power and signal paths without increasing chip footprint, thus resolving cross-talk issues while maintaining area efficiency.
2Reliability
If separate metal layers are used for power supply wires and data bus wires, then cross-talk and voltage drops are reduced, but production cost increases due to additional metal layers
Solution Approach 1:
The patent implements multi-functionality by designing the first power supply metal layer to serve dual purposes: it provides power supply connections during normal operation and acts as a shield against external electromagnetic interference. This universal design approach maximizes the utility of each metal layer, reducing the need for additional dedicated shielding layers and thereby controlling production costs while maintaining power integrity.
Solution Approach 2:
The patent introduces ground wires as intermediary elements positioned between signal transmission lines and external interference sources. These ground wires act as mediators that provide a low-impedance reference potential and divert electromagnetic interference, thereby protecting sensitive signal lines without requiring complex filtering circuits or additional power layers, thus balancing power integrity with manufacturing simplicity.
3Reliability
If ground wires are added to shield against external interference, then signal integrity improves, but chip area and device complexity increase
Solution Approach 1:
The patent merges the shielding function with existing structural elements by configuring the first power supply metal layer to simultaneously serve as both a power distribution network and an electromagnetic shield. By combining these two functions into a single layer, the patent eliminates the need for separate dedicated shielding layers, thereby maintaining signal integrity while avoiding increases in chip area and wiring complexity.
Solution Approach 2:
The patent enables the power supply network to serve its own shielding function through strategic placement and configuration of the first power supply metal layer. This self-service approach allows the power distribution infrastructure to provide both electrical power and electromagnetic protection, eliminating the need for additional specialized shielding components and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces cross-talk effects and voltage drops, improving signal integrity and power efficiency while maintaining cost and area efficiency, by creating parallel current paths and shielding effects without increasing chip size or production costs.
Implementation Method 1
a first power supply wire extending from the interface logic block to the array control logic block along a first path and supplied with a first power, a second power supply wire extending from the interface logic block to the array control logic block along a second path different from the first path and supplied with a second power
Implementation Method 2
At least one of the configuration bus lines is used as a shielding wire for shielding external interferences from the data bus lines
Data Source
AI summary
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.