Idle Power Control in Multi-Display Video Subsystems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing video subsystems consume significant power due to the maximum memory clock frequency being maintained even during periods of non-use or low activity, as the DRAM interface is not free for sufficient duration to retrain and lower the frequency, leading to inefficient power management.
Innovation Solution
The system rearranges data across multiple memory channels to identify and retrain idle channels by dividing screens into horizontal bars, allowing for the reduction of memory clock frequency and phase changes during periods of user inactivity or low activity, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory clock frequency is reduced to lower power consumption, then power usage decreases, but the DRAM interface is not free for sufficient duration to retrain the interface
Solution Approach 1:
The patent segments the display screen into multiple horizontal bars, with each bar assigned to a different memory channel. This segmentation allows the system to access only the specific memory channel corresponding to the current horizontal bar being displayed, leaving other channels idle and available for retraining operations without affecting overall display performance.
Solution Approach 2:
The system performs retraining operations on memory channels during idle periods before they are needed for display updates. By proactively retraining channels when they are not currently being used, the system ensures channels are ready for immediate use when required, avoiding delays in power management transitions.
2Use of energy by stationary object
If the MCLK frequency is lowered during low activity periods, then power consumption is reduced, but the interface requires retraining which takes time
Solution Approach 1:
The patent applies different operational states to different memory channels based on their current usage. Active channels maintain high MCLK frequency for optimal data rate, while idle channels are retrained and switched to lower frequency states for power savings. This localized quality adjustment optimizes both performance and power consumption dynamically.
Solution Approach 2:
The system dynamically adjusts the MCLK frequency for each memory channel based on real-time usage conditions. Channels transition between high-frequency active states and low-frequency idle states as needed, allowing the system to adapt power consumption levels to actual workload requirements while maintaining data integrity through periodic retraining.
3Speed
If multiple memory channels are used for high bandwidth, then data rate increases, but power consumption increases during idle periods
Solution Approach 1:
By dividing the display into horizontal bars and assigning each bar to a specific memory channel, the system activates only the necessary channels for current display updates. This segmentation enables selective power management where unused channels can be retrained and placed in low-power states, reducing overall power consumption while maintaining high bandwidth capability when needed.
Solution Approach 2:
The system implements periodic retraining of memory channels during idle periods between display updates. This periodic maintenance allows channels to be switched to lower power states temporarily, with retraining occurring in the background during natural idle windows, thus reducing average power consumption without compromising data rate when channels are actively needed.
Data Source
AI summary
A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency.