Idle-Prioritized Memory Ranks for DRAM Power Reduction

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Solution Overview

Problem

Dynamic random access memory (DRAM) power consumption is significant, and while low-power modes reduce background power, they result in high exit latencies when returning to active mode, impacting overall platform power efficiency.

Innovation Solution

Implementing a rank-aware cache replacement policy and control logic to selectively prioritize memory ranks for idleness, redirecting memory traffic to allow ranks to enter low-power modes for longer periods, thereby reducing access frequency and increasing energy efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If DRAM enters deeper low-power modes to conserve energy during idle periods, then power consumption is reduced, but exit latency increases when returning to active mode

Engineering Contradiction:

ImproveDRAM power consumptionVSAvoidDRAM exit latency

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The memory system is divided into multiple memory ranks (e.g., Rank 0, Rank 1, Rank 2, Rank 3), each capable of independent power state management. This segmentation allows the system to apply different power policies to different ranks based on their access patterns, enabling some ranks to enter deeper low-power modes while others remain active, thus balancing power savings with latency requirements

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic power state management where memory ranks can transition between different power states (active, idle, deep-sleep) based on real-time access patterns. The system dynamically adjusts which ranks enter low-power modes and for how long, adapting to changing workload characteristics to optimize the trade-off between power consumption and exit latency

Inventive Principle:

Principle #15Dynamics

2Productivity

If cache replacement policy is improved to reduce cache miss ratios, then memory access efficiency is enhanced, but system complexity increases

Engineering Contradiction:

Improvememory access efficiencyVSAvoidcache replacement policy complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies different cache replacement policies to different memory ranks based on their specific characteristics and access patterns. Instead of using a uniform replacement policy for all ranks, the system tailors the replacement strategy to each rank's workload, improving cache efficiency for each rank while managing overall system complexity through localized optimization

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system incorporates feedback mechanisms that monitor cache miss ratios and memory access patterns to dynamically adjust replacement policies. By continuously measuring performance and adapting the policy based on observed behavior, the system achieves improved memory access efficiency without requiring overly complex static replacement strategies

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS8484418B2Methods and apparatuses for idle-prioritized memory ranks

Publication Date: 2013.07.09 TAHOE RES LTD

AI summary

Embodiments of an apparatus to reduce memory power consumption are presented. In one embodiment, the apparatus comprises a cache memory, a memory, and a control unit. In one embodiment, the memory includes a plurality of memory ranks. The control unit is operable to select one or more memory ranks among the plurality of memory ranks to be idle-prioritized memory ranks such that access frequency to the idle-prioritized memory ranks is reduced.