Intelligent electronic device and method thereof

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing Intelligent Electronic Devices (IEDs) lack an efficient and manageable communication protocol between the Central Processing Unit (CPU) and Digital Signal Processor (DSP), which hampers effective data transmission and synchronization.

Innovation Solution

A transmission protocol is established between the CPU and DSP using a data header and payload, incorporating a field for command identification and direction, along with time synchronization methods to align the CPU's power grid time with the DSP's free-running counter time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a transmission protocol with data header and payload is implemented between CPU and DSP, then data transmission efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidcommunication protocol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The communication data is segmented into distinct components: a data header containing command identification and type fields, and a data payload containing the actual command or response data. This segmentation allows for structured and efficient communication between CPU and DSP, improving data transmission efficiency while maintaining manageable complexity through clear data organization.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If time synchronization between CPU and DSP is implemented using power grid time and free running counter, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvetime synchronization precisionVSAvoidtime synchronization mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary time synchronization mechanism that uses power grid time as a reference and implements a free running counter in the DSP. The CPU and DSP exchange time information through defined communication protocols, allowing precise time synchronization without requiring complex hardware modifications. This intermediary approach enables accurate timing for power monitoring and quality analysis.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If command identification and type fields are added to the data header, then ease of operation is improved, but device complexity increases

Engineering Contradiction:
Improvecommunication command managementVSAvoiddata header structure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The data header is designed with specific fields having particular functions: command identification fields for distinguishing different command types, and command type fields for indicating communication direction and frequency. This localized structuring of information allows for easy command management and processing while keeping the overall data header structure simple and standardized for CPU-DSP communication.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12360143B2Intelligent electronic device and method thereof
Publication Date: 2025.07.15 ACCUENERGY (CANADA) INC
  • US12360143B2 patent drawing
  • US12360143B2 patent drawing
  • US12360143B2 patent drawing

AI summary

Provided are a method and apparatus for communication between a CPU and a Digital Signal Processor (DSP) in an Intelligent Electronic Device (IED). Specifically, the IED includes at least one analog-to-digital converter coupled to at least one sensor and configured for converting an analog signal output from the at least one sensor to digital data; a DSP coupled to the at least one analog-to-digital converter, and configured to perform digital signal processing on the signal from the at least one analog-to-digital converter; a CPU coupled to the DSP via a hardware path; wherein the DSP and the CPU are configured to communicate using a transmission protocol including a data header and a data payload based on the hardware path; wherein the data header includes a field of command identification indicating a specific communication purpose and a field of command type indicating the communication direction and frequency.