Intelligent Electronic Device Memory Structure Preventing Data Loss

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Solution Overview

Problem

Intelligent electronic devices (IEDs) face challenges in preventing data loss during power outages due to limitations in existing non-volatile memory solutions, such as EEPROMs, NVRAMs, and FLASH memory, which incur delays and have limited write-erase cycles, leading to potential data loss and increased costs with battery backup systems.

Innovation Solution

Employing a dual-memory structure using a high-capacity FLASH memory for long-term storage and a ferroelectric random access memory (FRAM) or magnetoresistive random access memory (MRAM) for faster write performance and increased write-erase cycles, allowing for rapid data storage without battery backup, with FRAM capable of up to 10^10 operations and data retention for at least 10 years.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If EEPROM is used for non-volatile memory storage, then data retention without power is achieved, but write operation time is significantly delayed

Engineering Contradiction:
Improvedata retentionVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory system is segmented into two distinct types: volatile memory (RAM) for fast write operations and non-volatile memory (EEPROM/FLASH) for data retention. This segmentation allows each memory type to operate in its optimal performance regime, with RAM handling frequent writes and non-volatile memory preserving data across power cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Data is preliminarily written to volatile RAM memory during normal operation, and then periodically or on-demand transferred to non-volatile EEPROM memory. This preliminary action in fast memory prevents data loss while avoiding the penalty of slow write speeds, as the critical write operation occurs in the faster medium before verification in the slower medium.

Inventive Principle:
Principle #10Preliminary action

2Speed

If battery-backed RAM or NVRAM is used, then fast write performance is maintained, but device complexity and cost increase due to battery requirements

Engineering Contradiction:
Improvewrite speedVSAvoidbattery backup system
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The battery backup component is extracted and removed from the system. Instead of using battery-backed RAM or NVRAM that require continuous power to maintain data, the invention uses standard volatile RAM combined with non-volatile EEPROM memory, eliminating the need for batteries while maintaining data retention capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system uses inexpensive, maintenance-free EEPROM and FLASH memory devices that do not require battery backups. These non-volatile memory devices are designed to retain data indefinitely without power, replacing the need for expensive and maintenance-prone battery-backed solutions.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Quantity of substance

If FLASH memory is used for large capacity storage, then storage capacity is increased, but write-erase cycle limitations reduce reliability

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite-erase cycle endurance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system dynamically manages write operations across multiple memory devices with different characteristics. FLASH memory handles infrequent bulk storage operations where its high capacity is advantageous, while EEPROM handles more frequent updates. This dynamic allocation optimizes the utilization of each memory type's strengths and mitigates their weaknesses.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by using different memory devices for different types of data access patterns. FLASH memory is used for large-capacity, infrequent writes, while EEPROM is used for smaller, more frequent updates. This parameter-based allocation extends the effective write-erase cycle life of the overall storage system.

Inventive Principle:
Principle #35Parameter changes

4Device complexity

If single memory type is used, then device complexity is reduced, but inability to simultaneously achieve fast writes and data retention creates performance limitation

Engineering Contradiction:
Improvememory structureVSAvoiddata storage performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system merges volatile RAM memory and non-volatile EEPROM/FLASH memory into a unified memory architecture. This combination allows the system to leverage the fast write speeds of RAM and the data retention capabilities of non-volatile memory, achieving both speed and reliability in a single integrated solution.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory subsystem is designed with multi-functionality, where different memory devices serve different purposes within the same system. RAM provides fast temporary storage and processing, while EEPROM and FLASH provide persistent storage. This universal memory architecture can handle both time-critical and persistence-critical operations without requiring separate systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9927470B2Intelligent electronic device having a memory structure for preventing data loss upon power loss
Publication Date: 2018.03.27 ELECTRO INDUSTRIES GAUGE TECH
  • US9927470B2 patent drawing
  • US9927470B2 patent drawing
  • US9927470B2 patent drawing

AI summary

An intelligent electronic device is provided including, inter alia, a processing unit configured to calculate energy consumed by at least one load and accumulate the calculated energy in a first volatile memory; the processing unit being configured to iteratively copy the accumulated energy from the first volatile memory to a first non-volatile memory after a first predetermined time period and copy the accumulated energy from the first volatile memory to a second non-violate memory after a second predetermined time period, wherein the first predetermined time period is longer than the second predetermined time period. The processing unit is further configured to copy the accumulated energy from the second non-violate memory to the first volatile memory upon startup or reset of the intelligent electronic device to avoid loss of data.