IGBT Accumulation Region Layout for Lower On-Voltage and Turn-Off Loss
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Solution Overview
Problem
Conventional insulated gate bipolar transistors (IGBTs) face challenges in reducing on-voltage and turn-off loss due to limitations in carrier injection enhancement and depletion layer extension, particularly in the design of the N+ type accumulation region between the P type base layer and N type drift layer.
Innovation Solution
The semiconductor device incorporates an N+ type accumulation region with a high doping concentration between the P type base region and N type drift region, along with a P+ type collector region and N+ type buffer region, to enhance carrier injection and reduce on-voltage, and includes trench portions and a mesa structure to facilitate quick depletion and minimize turn-off loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If an N+ type accumulation region is provided between the P type base layer and N type drift layer to enhance carrier injection, then on-voltage is reduced, but turn-off loss increases due to extended depletion layer
Solution Approach 1:
The accumulation region is divided into multiple regions with different doping concentrations (first accumulation region with higher concentration and second accumulation region with lower concentration). This segmentation allows the first region to enhance carrier injection for lower on-voltage while the second region limits depletion layer extension to reduce turn-off loss.
Solution Approach 2:
Different regions of the accumulation layer are assigned different doping concentrations to perform different functions. The first accumulation region near the base layer uses high doping concentration for carrier injection enhancement, while the second accumulation region uses lower doping concentration to control depletion layer extension, creating local quality variations that resolve the contradiction.
2Reliability
If the doping concentration of the accumulation region is increased to improve carrier injection efficiency, then on-voltage decreases, but the depletion layer extends further increasing turn-off loss
Solution Approach 1:
The accumulation region is segmented into two distinct doping concentration zones. The first accumulation region has a doping concentration of 1×10^19 to 1×10^21 atoms/cm³ for high carrier injection efficiency, while the second accumulation region has a doping concentration of 1×10^17 to 1×10^19 atoms/cm³ to limit depletion layer extension and reduce turn-off loss.
Solution Approach 2:
The doping concentration parameter is changed across different regions of the accumulation layer. By varying the doping concentration from high in the first accumulation region to lower in the second accumulation region, the patent optimizes both carrier injection efficiency and turn-off loss characteristics simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves carrier injection efficiency, reduces on-voltage, and enhances the semiconductor device's turn-off performance by concentrating the electric field and preventing depletion layer extension, thereby improving the device's withstand capability and reducing turn-off loss.
Implementation Method 1
an N+ type accumulation region with a high doping concentration between the P type base region and N type drift region, along with a P+ type collector region and N+ type buffer region, to enhance carrier injection and reduce on-voltage
Implementation Method 2
includes trench portions and a mesa structure to facilitate quick depletion and minimize turn-off loss
Data Source
AI summary
Provided is an insulated gate bipolar transistor including: a base region which is provided between an emitter region and a drift region; an accumulation region which is provided between a base region and a drift region, and which has a doping concentration higher than that of the drift region; a gate trench portion which is provided from an upper surface of a semiconductor substrate to a portion below the accumulation region; and a lower end region which is provide to be in contact with a lower end of the gate trench portion; wherein the accumulation region has a first concentration peak in which the doping concentration indicates a maximum value in a depth direction, and a distance between the first concentration peak and the lower end region in a depth direction is less than a distance between the first concentration peak and the base region in the depth direction.