IGBT Barrier Region Segmentation for On-Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing IGBT technologies face challenges in reducing on-resistance while maintaining sufficient space for emitter and ion implantation regions, leading to increased processing costs and time due to the narrow mesa width between trench gates.
Innovation Solution
Incorporating a barrier region with a high concentration impurity of the first conductivity type between adjacent trench gates, which divides the mesa width and forms first and second current paths, allowing for easier accumulation of hole carriers and subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the mesa between adjacent trench gates is reduced to induce hole carrier accumulation, then conductivity modulation is maximized and on-resistance is reduced, but the space for forming emitter, ion implantation region, and pad is insufficient, increasing processing complexity and cost
Solution Approach 1:
The mesa region between adjacent trench gates is segmented by introducing a barrier region that divides the mesa width. This segmentation creates distinct zones: a first current path between the trench gate and barrier region, and a second current path between the barrier region and adjacent trench gate. The barrier region itself has a high concentration impurity region that facilitates hole carrier accumulation. This segmentation allows the effective width for conductivity modulation to be reduced while maintaining sufficient total space for emitter, ion implantation region, and pad formation, thereby resolving the contradiction between maximizing conductivity modulation and ensuring ease of manufacture.
2Reliability
If the width of the mesa between adjacent trench gates is reduced to induce hole carrier accumulation, then on-resistance is reduced, but the distance between trench gates becomes too short, making subsequent processing difficult and increasing processing time
Solution Approach 1:
The barrier region divides the mesa width into segmented current paths, allowing the effective width for hole carrier accumulation to be reduced (improving on-resistance) while the overall distance between trench gates remains sufficient for processing. The segmented structure provides clear spatial zones for emitter and ion implantation region formation, reducing processing time and complexity.
3Reliability
If the width of the mesa between adjacent trench gates is reduced to induce hole carrier accumulation, then conductivity modulation is maximized, but the space for emitter and ion implantation region formation is insufficient
Solution Approach 1:
The barrier region segments the mesa width, creating a structured division where the high concentration impurity region within the barrier provides the necessary hole carrier accumulation for conductivity modulation, while the segmented current paths maintain adequate spacing for emitter and ion implantation region formation. This resolves the spatial conflict between maximizing conductivity modulation and ensuring sufficient area for component formation.
4Ease of manufacture
If multiple barrier regions are introduced between adjacent trench gates, then sufficient space is secured for subsequent processing and hole carrier accumulation is facilitated, but device structure becomes more complex
Solution Approach 1:
The barrier region introduces a single, well-defined segmentation element between adjacent trench gates. This segmentation provides sufficient space for subsequent processing operations while facilitating hole carrier accumulation through the high concentration impurity region. The controlled introduction of this segmentation element improves ease of manufacture without excessively increasing device complexity, as the barrier region follows a regular pattern between trench gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-resistance, maximizes conductivity modulation, and facilitates faster switching speeds by securing sufficient space for emitter formation and reducing processing complexities.
Implementation Method 1
a bipolar transistor in which a barrier region in a mesa in the space between adjacent trench gates divides the width of the mesa, thereby inducing the accumulation of hole carriers (i.e., holes), and thus reducing an on-resistance
Implementation Method 2
forming an ion implantation region having a first conductivity type with a concentration higher than that of the impurity concentration in the body region
Data Source
AI summary
The present disclosure relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor, in which a barrier region is in a mesa between adjacent trench gates to divide the width of the mesa, thereby inducing the accumulation of hole carriers, and thus reducing an on-resistance (e.g., of the IGBT).