IGBT Buffer and Defect Layer Impurity Profiles
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Solution Overview
Problem
Conventional semiconductor devices, such as IGBTs, face challenges in reducing collector-emitter saturation voltage (VCE(sat)) and switching power loss, which are essential for improved performance in power conversion devices.
Innovation Solution
A semiconductor device structure with a specific impurity concentration profile in the buffer and defect layers, including a higher impurity concentration buffer layer with two peaks and a defect layer formed by ion implantation and annealing, reduces VCE(sat) and power loss. The defect layer is formed with an impurity concentration profile having a half-value width of not more than 2 μm, and particles like 4He, 3He, H, P, F, Ar, As, Sb, and Si are used to create crystal defects, optimizing the device's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional IGBT structure is used, then manufacturing is simpler, but VCE(sat) and power loss cannot be reduced sufficiently
Solution Approach 1:
The patent applies parameter changes by precisely controlling impurity concentration profiles in the buffer layer and drift layer. The buffer layer has a first impurity concentration profile with a peak near the collector layer interface, while the drift layer has a second impurity concentration profile with a peak near the emitter layer interface. This parameter optimization reduces carrier lifetime to minimize power loss while maintaining breakdown voltage requirements.
Solution Approach 2:
The patent implements local quality by creating spatially varying impurity concentrations within layers. The buffer layer exhibits higher impurity concentration near the collector layer interface that decreases toward the drift layer interface. The drift layer shows lower impurity concentration near the buffer layer interface that increases toward the emitter layer interface. This local quality variation optimizes both power loss and breakdown voltage characteristics.
2Loss of energy
If conventional buffer layer structure is used, then manufacturing is easier, but VCE(sat) cannot be reduced
Solution Approach 1:
The patent changes the impurity concentration parameter in the buffer layer by introducing a peaked profile with maximum concentration near the collector layer interface. This differs from conventional uniform or linear profiles. The peak position and concentration value are optimized to reduce VCE(sat) by controlling carrier distribution and reducing on-resistance while maintaining breakdown voltage.
Solution Approach 2:
The patent creates a composite impurity structure where the buffer layer and drift layer have complementary impurity profiles. The buffer layer's peaked profile combines with the drift layer's inverted profile to create an overall optimized carrier distribution. This composite approach allows simultaneous optimization of VCE(sat) and breakdown voltage that cannot be achieved with single-layer modifications.
3Loss of energy
If defect layer with wide impurity profile is used, then manufacturing is easier, but switching power loss increases
Solution Approach 1:
The patent precisely controls the defect layer's impurity concentration profile half-value width to be 2 μm or less. This narrow width parameter is critical for reducing switching power loss by creating localized carrier generation regions that minimize tail current effects. The precise parameter control requires advanced ion implantation or diffusion processes but delivers significant power loss reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure achieves lower VCE(sat) and power loss, enhancing the semiconductor device's efficiency and reliability, particularly in power conversion applications, by effectively controlling carrier lifetime and improving withstand voltage and switching characteristics.
Implementation Method 1
a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 μm in regard to a depth direction from the rear surface of the semiconductor substrate
Implementation Method 2
The semiconductor device may be manufactured by a method for manufacturing a semiconductor device that includes a process of forming the base layer of the second conductivity type on a front surface portion of the semiconductor substrate
Data Source
AI summary
A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 μm in regard to the depth direction from the rear surface of the semiconductor substrate.