IGBT Buffer Layer Design for Low ON Voltage and Switching Losses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in maintaining low ON voltage and reducing switching losses while ensuring high breakdown voltage and high-speed switching characteristics, particularly in IGBTs with thin wafer thicknesses, where defects and oscillations in voltage-current waveforms are concerns.
Innovation Solution
The semiconductor device features a structure with p-type base regions extending over the entire surface layer in mesa regions between trenches, increasing channel density and carrier injection, and a two-layer buffer structure with proton-doped and phosphorus-doped regions to control carrier distribution and reduce switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the excess carrier amount is increased to lower the resistance value of the drift layer, then the ON voltage is reduced, but the turn-off losses increase due to excess carriers needing to be swept out or annihilated
Solution Approach 1:
The patent applies local quality by creating distinct regions with different carrier concentrations within the drift layer. A first region has a higher carrier concentration to reduce ON voltage, while a second region has a lower carrier concentration to facilitate faster carrier removal during turn-off, thereby reducing turn-off losses. This spatial differentiation of carrier concentration properties resolves the trade-off between low ON voltage and low turn-off losses.
2Speed
If the wafer thickness is reduced to improve switching speed, then the switching losses are reduced, but defects and oscillations in voltage-current waveforms occur
Solution Approach 1:
The patent implements beforehand cushioning by introducing a buffer layer between the drift layer and the contact layer. This buffer layer acts as a cushion that prevents defects and oscillations from propagating through the device during switching operations. The buffer layer absorbs and mitigates the harmful effects of thin wafer thickness, allowing fast switching to be achieved without compromising waveform stability.
3Use of energy by moving object
If the carrier concentration on the collector side is decreased and on the emitter side is increased to optimize carrier distribution, then the trade-off between ON voltage and turn-off losses is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the drift layer into multiple regions with different carrier concentrations. The first region has a higher carrier concentration optimized for low ON voltage, while the second region has a lower carrier concentration optimized for fast turn-off. This segmentation of the drift layer into functionally distinct zones enables independent optimization of both ON voltage and turn-off losses without requiring complex overall device redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains low ON voltage, reduces switching losses, and suppresses oscillations in voltage-current waveforms, allowing for thinner wafer thicknesses and improved trade-off relationships between ON voltage and switching losses.
Implementation Method 1
a first buffer layer with a proton-doped region having a first carrier concentration
Implementation Method 2
a second buffer layer with a phosphorus-doped region having a second carrier concentration
Implementation Method 3
IGBTs (Insulated Gate Bipolar Transistors) of a voltage drive type, which realize a low ON voltage by a conductivity modulation effect
Data Source
AI summary
A plurality of trenches is provided in a stripe shape extending in a direction parallel to a substrate front surface to a predetermined depth in a depth direction. A gate electrode is provided inside each trench, with a gate insulating film interposed there between. In mesa regions separated by the trenches, p-Type base regions at an emitter potential are provided over the entire surface layer on the substrate front surface side. Inside the p-type base regions, n+-type emitter regions are provided dispersedly at a predetermined interval in the longitudinal direction of the trenches. A p-type collector layer and an n+-type buffer layer are provided in this order on the surface layer of the substrate back surface. The thickness of the n+-type buffer layer is substantially equal to or larger than the thickness of an n−-type drift layer. As a result, switching losses are reduced while maintaining an ON voltage.