IGBT Buffer Layer Doping for Latch-up Prevention
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Solution Overview
Problem
Insulated Gate Bipolar Transistors (IGBTs) face issues with parasitic PNPN thyristor latch-up, which limits their safe operating area and can cause damage due to excessive current flow, as the gate loses its ability to turn off, especially when the current gain of NPN and PNP transistors is 1 or more.
Innovation Solution
The IGBT design includes a collector ion implantation area, first and second segment buffer layers, base areas, and emitter ion implantation areas, with specific ion implantation processes to form a poly layer and buffer layers of different conductive types, reducing electrical resistance and preventing latch-up by controlling hole current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the current gain sum of NPN and PNP transistors is increased to improve power handling capability, then the power handling capability is improved, but parasitic thyristor latch-up occurs and the gate loses its ability to turn off
Solution Approach 1:
The patent extracts and removes the parasitic PNPN thyristor structure from the IGBT by eliminating the P-base region that enables thyristor formation. This is achieved through a specific doping profile where the P-type base doping concentration is reduced or eliminated in certain regions, thereby preventing the formation of the parasitic thyristor while maintaining the necessary bipolar transistor functionality for power handling.
Solution Approach 2:
The patent changes the doping concentration parameters of the base region, specifically reducing the P-type base doping concentration to prevent parasitic thyristor latch-up. By adjusting these doping parameters, the device maintains high current gain for power handling while preventing the conditions that lead to latch-up phenomena.
2Loss of energy
If the forward voltage drop is reduced to improve efficiency, then the power consumption is reduced, but the device may become more susceptible to latch-up phenomena
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in different regions of the device. The emitter region has high doping concentration to reduce forward voltage drop and improve efficiency, while the base region has reduced or optimized doping concentration to prevent latch-up. This spatial variation in doping quality allows simultaneous optimization of both efficiency and reliability.
Solution Approach 2:
The patent optimizes the doping concentration parameters across different regions to achieve low forward voltage drop while preventing latch-up. Specifically, the emitter doping is increased to reduce voltage drop, while the base doping is optimized to maintain stability and prevent parasitic thyristor formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes forward voltage drop and prevents parasitic thyristor latch-up, allowing for safer operation and reduced power consumption by optimizing current flow and reducing latch-up currents.
Implementation Method 1
Forming a collector ion implantation area within a substrate by implanting ions of a first conductive type. Forming first buffer layers, each including a first segment buffer layer and a second segment buffer layer, on and/or over the collector ion implantation area by implanting ions of a second conductive type. Forming base areas in the substrate on and/or over the first buffer layer by implanting ions of the first conductive type. Forming emitter ion implantation areas within the base areas, respectively, by implanting ions of the second conductive type.
Data Source
AI summary
According to embodiments, an insulated gate bipolar transistor (IGBT) may include a first conductive type collector ion implantation area, formed within a substrate, second conductive type first buffer layers, formed over the collector ion implantation area and each including a first segment buffer layer and a second segment buffer layer, a first conductive type poly layer formed from a surface of the substrate to the collector ion implantation area, the first conductive type poly layer having a contact structure, a second buffer layer of the second conductive type, formed in the substrate area next to the first conductive type poly layer. According to embodiments, a segment buffer layer may have different concentrations according areas. Accordingly, amounts of hole currents injected through the buffer layers may differ according to areas.