Gate Busbar Segmentation for Uniform IGBT Cell Signal Timing
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Solution Overview
Problem
In power semiconductor devices, especially IGBTs, the parasitic parameters of the gate busbar cause signal delay and uneven current distribution, particularly under high frequency applications, due to the increasing size of power chips with more cells connected in parallel.
Innovation Solution
A semiconductor device design featuring emitter segments with non-uniform lengths and a gate busbar with non-uniform widths or thicknesses to ensure consistent gate signal delivery to each cell, achieved by varying the widths or thicknesses of the gate busbar portions along specific axes to match the distance from the gate pad, thereby reducing signal differences between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the power chip size is increased to accommodate more cells connected in parallel, then the power handling capability is improved, but the parasitic parameters of the gate busbar increase causing signal delay and uneven current distribution
Solution Approach 1:
The gate busbar is designed with non-uniform width or thickness, where the width/thickness varies along its length to compensate for the increased distance to cells. Specifically, the gate busbar has a larger width or thickness near the gate pad and gradually decreases toward the periphery, creating local variations in electrical properties to balance the signal arrival time across all cells despite the increased chip size
2Power
If the power chip size is increased to accommodate more cells connected in parallel, then the power handling capability is improved, but the current distribution uniformity deteriorates
Solution Approach 1:
The gate busbar employs non-uniform cross-sectional dimensions (width or thickness) to create localized electrical property variations. This design ensures that cells farther from the gate pad receive equivalent gate signal strength as closer cells, achieving uniform current distribution across the enlarged chip area
3Reliability
If the gate busbar width is increased to reduce parasitic resistance, then the signal transmission is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of using a uniformly wide gate busbar, the invention changes the geometric parameters (width or thickness) of the gate busbar along its length. This parameter variation allows optimization of electrical performance while maintaining a relatively simple single-layer busbar structure that is compatible with standard semiconductor manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures that each cell receives a consistent gate signal, improving current sharing capability and reducing signal delay, even at high frequencies, by adjusting the resistance and length of the gate busbar to maintain uniform signal arrival times across the chip.
Implementation Method 1
widths or thicknesses of the plurality of first portions are different from each other... adjusting the resistance and length of the gate busbar to maintain uniform signal arrival times across the chip
Data Source
Figure 1~2
Figure 3a~4
Figure 5a~5b
AI summary
The present invention provides a semiconductor device having a plurality of cells, each of the plurality of cells includes a gate. The semiconductor device includes a gate pad, a gate busbar and a plurality of gate lines. The gate busbar connects the gate pad to the plurality of gate lines, the plurality of gate lines connects the gate busbar to the gates of the plurality of cells, and each of the plurality of gate lines is disposed along a first axis. The gate busbar includes a plurality of first portions each disposed along a second axis, the second axis intersects with the first axis. The plurality of first portions are spaced apart from each other to divide the semiconductor device into a plurality of emitter segments. Lengths of the plurality of emitter segments along the first axis changes with distances of the plurality of emitter segments from the gate pad, such that gate signals arriving at the gates of the plurality of cells from the gate pad via the gate busbar and the plurality of gate lines are substantially consistent.