IGBT Cell Layout for Cutoff Resistance at Chip Termination
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Solution Overview
Problem
Existing IGBT semiconductor devices face challenges with local current/electric field concentration and reduced cutoff resistance due to electric field variations between cells caused by manufacturing variations.
Innovation Solution
The semiconductor device incorporates a central area cell with a trench gate structure and specific impurity concentration layers, along with an outer peripheral area cell lacking certain impurity concentration layers, to suppress current and electric field concentration and enhance cutoff resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the high output current density is reached, then the power device output increases, but the chip temperature increases and the loss per unit chip area increases
Solution Approach 1:
The patent applies local quality by creating different cell structures in different regions of the IGBT chip. Central area cells contain all semiconductor layers (third through seventh layers) while outer peripheral area cells lack the third and seventh layers. This regional differentiation allows optimal performance in each zone: central cells provide high current density while peripheral cells suppress electric field concentration and improve cutoff resistance, enabling high power output without excessive temperature rise
2Reliability
If the current cutoff capability is improved by reducing hole injection in peripheral guard ring portion, then the parasitic bipolar transistor operation is suppressed, but the cutoff resistance may decrease when electric field variation occurs
Solution Approach 1:
The patent implements local quality by differentiating cell structures between central and peripheral regions. Central area cells include the third semiconductor layer (n-type) and seventh semiconductor layer (p-type) with high impurity concentrations to suppress electric field concentration and maintain stable cutoff resistance. Outer peripheral area cells exclude these layers to reduce hole injection and suppress parasitic bipolar transistor operation. This regional differentiation makes the device less sensitive to manufacturing variations
3Reliability
If the avalanche resistance of termination area is increased by removing trench structure, then the RBSOA is improved, but the electric field concentration may occur at termination portion
Solution Approach 1:
The patent applies local quality by creating different cell configurations in central versus peripheral regions. Outer peripheral area cells, located between central cells and the termination guard ring area, are designed without the third and seventh semiconductor layers. This structural differentiation allows the peripheral region to handle avalanche events more effectively by reducing electric field concentration at the termination portion while maintaining overall RBSOA improvement
4Area of stationary object
If the chip size is reduced, then the cost decreases, but the current density requirement becomes more challenging to meet
Solution Approach 1:
The patent enables higher current density in a compact chip area by optimizing different regions for different functions. Central area cells with complete layer structures maximize current carrying capacity, while outer peripheral area cells without the third and seventh layers suppress electric field concentration and improve cutoff resistance. This allows the chip to achieve high power output in a reduced area without compromising reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively improves the cutoff resistance of the IGBT semiconductor device, allowing for higher current density and contributing to the miniaturization of power conversion devices.
Implementation Method 1
a gate insulating film and insulated from the emitter electrode via the interlayer insulating film
Implementation Method 2
a third semiconductor layer of a second conductivity type formed in contact with the gate insulating film and having a higher impurity concentration than the semiconductor substrate; a fourth semiconductor layer of a first conductivity type formed in contact with a semiconductor substrate side of the emitter electrode via an emitter contact and having a higher impurity concentration than the first semiconductor layer
Data Source
AI summary
A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.