IGBT Cell Design for Safe Operating Area and On-State Losses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage Insulated-Gate Bipolar Transistor (IGBT) devices face challenges in achieving sufficient Safe Operating Area (SOA) and low on-state losses, especially for ratings above 2000 V, due to harsh SOA conditions and dynamic avalanche at low n-base doping levels.
Innovation Solution
The design incorporates additional well regions with higher doping concentrations outside the active cell, electrically connected to the emitter electrodes, which provide a hole barrier and alternative avalanche paths, reducing on-state losses and increasing latch-up immunity without affecting the active cell design or carrier profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If highly doped p+ well regions are added in the active cell region to increase latch-up immunity, then the safe operating area is improved, but on-state losses increase
Solution Approach 1:
The invention divides the well region into two distinct parts: additional well regions outside the active cell region and channel well regions within the active cell region. This segmentation allows the additional well regions to provide latch-up immunity and safe operating area improvement without interfering with the carrier profile optimization in the active cell region, thus resolving the contradiction between improved reliability and reduced energy loss.
Solution Approach 2:
The invention applies different doping characteristics to different spatial locations: highly doped additional well regions are placed outside the active cell region to provide hole barrier and improve latch-up immunity, while the channel well regions within the active cell region are optimized for carrier profile. This local differentiation allows each region to perform its specific function optimally, achieving both improved safe operating area and low on-state losses.
2Reliability
If additional p+ well regions are added to improve safe operating area, then latch-up immunity increases, but device complexity increases
Solution Approach 1:
The invention merges the functions of latch-up immunity provision and safe operating area improvement into a single structural element: the additional well regions outside the active cell region. These regions simultaneously provide the hole barrier for latch-up immunity and serve as avalanche initiation points for improved safe operating area, thereby improving reliability without proportionally increasing device complexity.
3Loss of energy
If the n- base doping level is reduced to achieve low on-state losses, then on-state losses decrease, but dynamic avalanche occurs at lower current densities reducing safe operating area
Solution Approach 1:
The additional well regions act as an intermediary structure that mediates between the low doped n- base region and the requirements for safe operating area. By providing dedicated avalanche initiation points outside the active cell region, these additional well regions protect the low doped base region from dynamic avalanche effects, allowing the base doping to remain low for reduced on-state losses while maintaining adequate safe operating area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the turn-off capability and increases the critical latch-up current levels, achieving improved SOA and low on-state losses while maintaining optimal carrier profiles and design rules.
Implementation Method 1
additional well regions with higher doping concentrations outside the active cell, electrically connected to the emitter electrodes, which provide a hole barrier and alternative avalanche paths
Implementation Method 2
additional well regions with higher doping concentrations outside the active cell, electrically connected to the emitter electrodes, which provide a hole barrier and alternative avalanche paths
Data Source
Figure 1
Figure 2
Figure 3~7
AI summary
An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced safe operating are capability. The additional well regions (11) outside the active cell (5) do not affect the active cell design in terms of cell pitch, i.e. the design rules for cell spacing, and hole drainage between the cells, hence resulting in optimum carrier profile at the emitter side for low on-state losses.