IGBT Cell Pitch Optimization for On-Voltage Reduction
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Solution Overview
Problem
Existing semiconductor devices, such as IGBTs, face challenges in reducing on-voltage, which is critical for minimizing power loss, particularly due to the optimization of IGBT cell pitch in relation to the base layer thickness affecting blocking voltage.
Innovation Solution
The semiconductor device optimizes the pitch of IGBT cells based on the distance between specific semiconductor regions, setting it between 1/40 and 1/20 of the distance between the second and fourth semiconductor regions to lower on-voltage across various blocking voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the pitch of IGBT cells is optimized in accordance with the thickness of the base layer, then the on-voltage is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by establishing a specific quantitative relationship between the pitch of IGBT cells and the thickness of the base layer. The pitch is set to 1/40 or more and 1/20 or less of the distance between the second semiconductor region and the fourth semiconductor region, which corresponds to the base layer thickness. This parameter optimization reduces on-voltage by improving cell density while maintaining manufacturability through defined ranges rather than exact values.
Solution Approach 2:
The patent implements dynamics by making the pitch of IGBT cells variable rather than fixed. The pitch is dynamically adjusted in accordance with the thickness of the base layer, allowing the cell density to adapt to different base layer thicknesses. This dynamic relationship enables on-voltage reduction across various blocking voltage specifications while accommodating manufacturing variations.
2Loss of energy
If the pitch of IGBT cells is decreased to increase cell density, then the on-voltage is reduced, but the device complexity increases
Solution Approach 1:
The patent uses parameter changes by defining the pitch within specific ranges (1/40 to 1/20 of the distance between the second and fourth semiconductor regions) rather than using excessively small fixed values. This approach achieves on-voltage reduction through optimized cell density while avoiding the complexities associated with extremely fine-pitch structures, maintaining a balance between performance and device complexity.
Data Source
AI summary
Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.