IGBT Contact Region Layout to Suppress Parasitic Latchup
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Solution Overview
Problem
Semiconductor devices such as IGBTs face challenges in improving their latchup withstand capacity, particularly due to the potential rise in the p-type base region at the n+-type emitter region vicinity during hole discharge, which can lead to parasitic thyristor operation and breakdown.
Innovation Solution
The semiconductor device incorporates a p+-type contact region positioned next to the n+-type emitter region and a contact part extending through the insulating layer, reducing the potential rise and likelihood of parasitic thyristor operation by altering the impurity concentration and positioning of semiconductor regions, thereby enhancing latchup withstand capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If holes are discharged through the p-type base region at the n+-type emitter region vicinity, then the current conduction function is achieved, but the potential rises and causes parasitic thyristor operation leading to breakdown
Solution Approach 1:
A p+-type contact region is introduced as an intermediary structure between the n+-type emitter region and the p-type base region. This contact region serves as a mediator that provides an alternative low-resistance path for hole discharge, preventing potential rise in the p-type base region and suppressing parasitic thyristor operation.
Solution Approach 2:
The impurity concentration of the p+-type contact region is set to be higher than that of the p-type base region (second-conductivity-type impurity concentration of the fourth semiconductor region is greater than second-conductivity-type impurity concentration of the second semiconductor region). This parameter change creates a lower resistance path for hole discharge, effectively reducing potential rise and preventing latchup.
2Device complexity
If the p-type base region is positioned close to the n+-type emitter region for compact structure, then device integration is improved, but the likelihood of parasitic thyristor operation increases due to potential rise
Solution Approach 1:
The p+-type contact region acts as a protective intermediary layer between the closely positioned n+-type emitter region and p-type base region. Even when these regions are positioned close together for compact structure, the contact region maintains electrical stability by providing a preferred discharge path for holes, preventing parasitic thyristor operation.
Solution Approach 2:
The p+-type contact region is locally positioned at the critical interface between the emitter and base regions where potential rise occurs. By concentrating the high impurity concentration in this specific local area, the invention addresses the potential rise problem at the critical location without affecting the overall compact structure.
Data Source
AI summary
According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer. The third semiconductor region is located on the second semiconductor region. The fourth semiconductor region is located on the second semiconductor region. An impurity concentration of the fourth semiconductor region is greater than an impurity concentration of the second semiconductor region. The second electrode is located on the second, third, and fourth semiconductor regions. The second electrode includes a contact part. The fifth semiconductor region is located between the second semiconductor region and the contact part. An impurity concentration of the fifth semiconductor region is greater than the impurity concentration of the second semiconductor region.