Integrated IGBT-Diode Structure for Depletion Layer Isolation
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Solution Overview
Problem
Current semiconductor devices with integrated IGBT and diode structures face challenges in achieving efficient electrical isolation and unipolar operation due to the spreading of the depletion layer and current blocking, which affects their performance and reliability.
Innovation Solution
The semiconductor device incorporates a specific structure with a p+-type collector region, n-type buffer regions, and an oxygen implantation region with high oxygen concentration, which suppresses the depletion layer spreading and current flow, enabling effective electrical isolation and unipolar operation by reducing carrier lifetime and crystal defect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an IGBT and diode are integrated on a single semiconductor substrate, then device functionality is improved, but electrical isolation between regions deteriorates due to depletion layer spreading
Solution Approach 1:
The semiconductor substrate is divided into distinct first and second regions with different impurity concentration distributions. The first region has a first-conductivity-type impurity concentration that increases toward the surface, while the second region has a second-conductivity-type impurity concentration that decreases toward the surface. This segmentation creates natural electrical isolation between the IGBT and diode regions, preventing depletion layer spreading while maintaining integrated functionality.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different impurity concentration profiles tailored to their specific functional requirements. The first region (IGBT region) has increasing impurity concentration toward the surface to support high-current switching, while the second region (diode region) has decreasing impurity concentration to enable efficient minority carrier operation. This local quality differentiation achieves both functional integration and electrical isolation.
2Power
If impurity concentration is increased to improve current carrying capacity, then electrical conductivity is improved, but depletion layer spreading increases affecting electrical isolation
Solution Approach 1:
The patent applies different impurity concentration profiles to different regions: the first region has increasing first-conductivity-type impurity concentration toward the surface to enhance current carrying capacity for the IGBT, while the second region has decreasing second-conductivity-type impurity concentration toward the surface to maintain electrical isolation and support diode operation. This localized optimization resolves the contradiction between power capability and electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical resistance modulation and reduces unipolar operation, improving the semiconductor device's performance and reliability by effectively isolating the IGBT and diode regions.
Implementation Method 1
a third region located between the first region and the second region in a second direction perpendicular to a first direction that is from the first electrode toward the second electrode
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor part located between the first electrode and the second electrode. The semiconductor part includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to a first direction that is from the first electrode toward the second electrode. The third region includes a tenth semiconductor region of the first conductivity type located on the first electrode, and a current blocking region located between the sixth semiconductor region and the ninth semiconductor region in the second direction and located on the tenth semiconductor region.