IGBT-Diode Layer Structure for Higher Withstand Voltage

The patent applies local quality by creating different depth positions for carrier accumulation layers at different lateral positions. Specifically, the second carrier accumulation layer is formed at a shallower depth on the boundary side between IGBT and diode regions, while the first carrier accumulation layer is at a deeper position in the IGBT region. This spatial variation in depth creates localized field plate effects at the boundary while maintaining adequate voltage blocking in the IGBT region, thus resolving the contradiction between achieving field plate effect and preventing electric field concentration.

The patent resolves the contradiction by introducing depth as an additional dimensional parameter. Instead of uniform carrier accumulation layer depth, the invention varies the depth position of carrier accumulation layers in the vertical dimension while also considering lateral position. This creates a three-dimensional carrier accumulation structure where depth varies with lateral position, enabling simultaneous achievement of field plate effect at boundaries and voltage blocking in bulk regions.