IGBT Diode Cell Snap Back Suppression via Layer Resistivity
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Solution Overview
Problem
Semiconductor devices with IGBT and diode cells parallel-formed in a single substrate suffer from snap back phenomena in current-to-voltage characteristics, leading to unbalanced current distribution and operational issues in parallel connections, requiring suppression of snap back voltage below the threshold voltage.
Innovation Solution
A semiconductor device design where the resistivity and thickness of specific semiconductor layers are optimized to satisfy the relationship (ρ1/ρ2)×(L1·L2/W22)<1.6, reducing snap back voltage and preventing its occurrence, thereby ensuring stable parallel operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If IGBT cells and diode cells are parallel-formed in a single semiconductor substrate to make inverter circuits compact, then device integration and compactness are improved, but snap back phenomena occur causing unbalanced current distribution and operational issues
Solution Approach 1:
The patent introduces a field stop layer with specific resistivity characteristics localized between the drift layer and collector layer. This local structural modification creates different electrical field distribution characteristics in the IGBT cell region compared to conventional designs, thereby suppressing snap back phenomena and achieving balanced current distribution while maintaining compact integration with diode cells.
Solution Approach 2:
The patent specifies precise parameter relationships for the field stop layer resistivity (ρ2) relative to the drift layer resistivity (ρ1), expressed as 0.01 < (ρ1/ρ2) < 10. By controlling this resistivity ratio parameter along with layer thickness parameters, the patent optimizes the electrical characteristics to suppress snap back effects and ensure reliable parallel operation of multiple IGBT cells.
2Reliability
If snap back voltage is suppressed below threshold voltage through parameter optimization, then parallel operation stability is improved, but design complexity increases due to multiple parameter constraints
Solution Approach 1:
The patent establishes specific parameter ranges for the field stop layer resistivity ratio (0.01 < (ρ1/ρ2) < 10) and thickness relationships to suppress snap back phenomena. By defining these parameter boundaries, the patent provides clear design guidelines that ensure reliable parallel operation while managing design complexity through quantifiable constraints rather than trial-and-error approaches.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ1 and a thickness L1 of the first layer, a resistivity ρ2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (ρ1/ρ2)×(L1·L2/W22)<1.6.