IGBT Diode Voltage Management via Doping Optimization
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Solution Overview
Problem
Conventional IGBT modules experience increased loss due to avalanche current flow when the reverse withstand voltage of the IGBT is lower than the forward recovery voltage, leading to junction breakdown and high p-type emitter layer and n-type buffer layer steepness limitations.
Innovation Solution
The IGBT and diode are structured with specific doping concentrations and regions to ensure the forward recovery voltage is less than the reverse withstand voltage, using floating-zone-grown silicon crystals and ion implantation techniques, with additional n-type interposing layers to enhance reverse withstand voltage and reduce forward recovery voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reverse withstand voltage of the IGBT is made lower than the forward recovery voltage, then the device can operate in certain conditions, but avalanche current flows causing increased loss and potential breakdown
Solution Approach 1:
The patent applies parameter changes by optimizing the doping concentration of the n-type buffer layer and the thickness of the p-type emitter layer to achieve the desired voltage relationship (Vf < Vbr) while preventing avalanche current flow and reducing energy loss
2Ease of manufacture
If ion implantation is used to form the n-type buffer layer and p-type emitter layer, then the manufacturing process is established, but the junction steepness is limited causing reverse withstand voltage to be low
Solution Approach 1:
The patent changes the parameters of ion implantation including doping concentration, implantation energy, and layer thickness to achieve both ease of manufacture and improved junction steepness, thereby increasing reverse withstand voltage
3Loss of energy
If the p-type emitter layer is made thin to suppress hole injection and reduce turn-off loss, then switching loss is reduced, but the reverse withstand voltage capability is compromised
Solution Approach 1:
The patent optimizes the thickness parameter of the p-type emitter layer and compensates by adjusting the n-type buffer layer doping concentration, achieving both reduced turn-off loss through thin emitter layer and maintained reverse withstand voltage through buffer layer optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents avalanche current flow, achieving low-cost and low-loss semiconductor devices with improved reverse withstand and forward recovery voltage management.
Implementation Method 1
an n-type buffer layer 7 is formed by performing ion implantation on the other surface portion of the FZ crystal substrate, a p-type emitter layer 8 is formed by ion-implanting lightly
Data Source
AI summary
In a semiconductor device having a pair of IGBT and diode which are connected to each other in inverse-parallel in which a collector-electrode of the IGBT and a cathode-electrode of the diode are wired to each other, and an emitter-electrode of the IGBT and an anode-electrode of the diode are wired to each other, when a breakdown voltage of a junction of a p-type emitter layer and an n-type buffer layer of the IGBT is represented as BVec, and a forward voltage occurring while the diode transits from a state of blocking to a state of forward conduction is represented as VF, a relationship of VF<BVec is satisfied in a predetermined current value Id of a current flowing in the diode, and the maximal doping concentration of the n-type cathode layer of the diode is higher than that of the n-type buffer layer of the IGBT.