IGBT Extraction Region Carrier Control via Dummy Gate
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Solution Overview
Problem
Semiconductor devices with IGBTs face challenges in lowering ON voltage while maintaining or improving current breaking capability during turn-off operations, as introducing lattice defects in the extraction region can elevate ON voltage and affect current breaking performance.
Innovation Solution
A semiconductor device configuration with a P-type layer on an N-type drift layer in the extraction region, connected to the emitter electrode, and a dummy gate electrode via an insulation film, where the carrier lifetime in the termination region is shorter than in the transistor and extraction regions, allowing for reduced ON voltage and enhanced current breaking capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lattice defect is introduced in the extraction region to improve current breaking capability, then current breaking capability is improved, but ON voltage is elevated
Solution Approach 1:
The patent applies local quality by differentiating the treatment between regions: lattice defects are introduced only in the termination region while the extraction region maintains high crystal quality. This spatial differentiation allows the termination region to provide current breaking capability through defects while the extraction region maintains low ON voltage through high quality, resolving the contradiction between these two requirements.
Solution Approach 2:
The patent segments the device into distinct functional regions with different properties: the termination region contains lattice defects for current breaking, the extraction region has high crystal quality for low ON voltage, and the transistor region maintains optimal characteristics. This segmentation allows each region to optimize its specific function without compromising other regions.
2Reliability
If lattice defect is introduced in the termination region to improve current breaking capability, then current breaking capability is improved, but carrier lifetime is reduced
Solution Approach 1:
The patent applies local quality by introducing lattice defects specifically in the termination region where short carrier lifetime is beneficial for current breaking, while maintaining long carrier lifetime in the extraction and transistor regions where it is needed for low ON voltage and proper transistor operation. This spatially differentiated approach resolves the contradiction between requiring short lifetime in termination and long lifetime in other regions.
3Loss of energy
If the extraction region has high crystal quality to lower ON voltage, then ON voltage is lowered, but current breaking capability during turn-off is reduced
Solution Approach 1:
The patent resolves this contradiction by applying local quality differently to different regions: the extraction region maintains high crystal quality for low ON voltage, while the termination region introduces lattice defects for current breaking capability. The dummy gate electrode further enhances extraction region performance without compromising turn-off characteristics.
Solution Approach 2:
The dummy gate electrode acts as an intermediary structure that enhances carrier extraction in the high-quality extraction region during turn-off operations, enabling the extraction region to contribute to current breaking without requiring lattice defects that would increase ON voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively lowers ON voltage and improves current breaking capability during turn-off operations by controlling carrier concentration and field intensity, while minimizing leakage current and device breakdown.
Implementation Method 1
an extraction region placed between the transistor and the termination region and extracting redundant carriers
Implementation Method 2
lattice defect is introduced into the termination region and the extraction region. Since the carrier concentration during turn-off operation can be lowered thereby, depletion can be easily made, and field intensity can be reduced
Implementation Method 3
a dummy gate electrode is placed via an insulation film on the P-type layer, the dummy gate electrode is connected to the gate electrode
Implementation Method 4
a dummy gate electrode is placed via an insulation film on the P-type layer
Data Source
AI summary
A semiconductor device includes: a transistor region including an IGBT having a gate electrode and an emitter electrode; a termination region placed around the transistor region; and an extraction region placed between the transistor and the termination region and extracting redundant carriers. A P-type layer is placed on an N-type drift layer in the extraction region. The P-type layer is connected to the emitter electrode. A dummy gate electrode is placed via an insulation film on the P-type layer. The dummy gate electrode is connected to the gate electrode. Life time of carriers in the termination region is shorter than life time of carriers in the transistor region and the extraction region.