IGBT Field Stop Layer Impurity Peak Segmentation
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Solution Overview
Problem
Conventional IGBT devices face a challenge in achieving both reduced switching oscillation and improved large-current-induced short-circuit withstand capability, as these requirements conflict in terms of the characteristics needed for the field stop layer (FS layer) positioning and concentration.
Innovation Solution
The semiconductor device incorporates a semiconductor layer with impurity concentration peaks positioned differently along the thickness direction, including a field stop layer with proton-related impurity peaks, a buffer layer with higher impurity concentration, and a collector layer, optimized to reduce electric fields and enhance carrier implantation characteristics, allowing for both reduced oscillation and improved short-circuit withstand capability without trade-offs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the FS layer is positioned closer to the emitter electrode than normally and has a higher concentration, then the oscillation that may occur at the time of switching is reduced, but the large-current-induced short-circuit withstand capability deteriorates
Solution Approach 1:
The patent divides the FS layer into multiple impurity concentration peaks positioned at different locations within the drift layer. Instead of using a single concentrated FS layer, the invention segments the impurity concentration into multiple peaks (first peak closer to emitter, second peak closer to collector), allowing each peak to serve different functions: the first peak reduces switching oscillation while the second peak maintains short-circuit withstand capability.
Solution Approach 2:
The patent applies local quality by creating different impurity concentration characteristics at different positions within the drift layer. The first impurity concentration peak is positioned closer to the emitter electrode with specific concentration characteristics to reduce oscillation, while the second impurity concentration peak is positioned closer to the collector electrode with different concentration characteristics to maintain short-circuit withstand capability. Each local region has optimized properties for its specific function.
2Reliability
If the FS layer is positioned closer to the collector electrode, then the large-current-induced short-circuit withstand capability is improved, but the oscillation that may occur at the time of switching increases
Solution Approach 1:
The patent segments the FS layer functionality into multiple impurity concentration peaks. The second peak positioned closer to the collector electrode maintains short-circuit withstand capability, while the first peak positioned closer to the emitter electrode addresses the switching oscillation issue. This segmentation allows the system to achieve both requirements simultaneously.
Solution Approach 2:
The patent creates localized impurity concentration peaks with different characteristics at different positions. The region closer to the collector electrode has impurity characteristics optimized for short-circuit withstand capability, while the region closer to the emitter electrode has impurity characteristics optimized for reducing switching oscillation.
3Device complexity
If a single FS layer configuration is used, then the device structure is simple, but it is difficult to achieve both reduced switching oscillation and improved short-circuit withstand capability
Solution Approach 1:
The patent segments the FS layer into multiple impurity concentration peaks within a single drift layer structure. This segmentation allows the device to achieve complex performance requirements (both reduced oscillation and improved short-circuit withstand capability) while maintaining a relatively simple overall structure of just two semiconductor layers.
Solution Approach 2:
The patent changes the impurity concentration parameters by creating multiple peaks with different concentration values and positions. The first peak has specific concentration and position parameters optimized for reducing oscillation, while the second peak has different parameters optimized for short-circuit withstand capability. This parameter variation allows simultaneous achievement of multiple performance goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces switching oscillation and enhances the large-current-induced short-circuit withstand capability by controlling impurity concentrations and peak positions, preventing depletion layer expansion and maintaining lower electric fields, thus improving overall device performance.
Implementation Method 1
The semiconductor layer of the first conductivity type has a plurality of impurity concentration peaks that are differently positioned in a first direction
Implementation Method 2
an insulated gate bipolar transistor (IGBT) device has a region doped with hydrogen ions and the like that may serve as a field stop layer (FS layer)
Data Source
AI summary
A semiconductor layer of a first conductivity type has a plurality of impurity concentration peaks that are differently positioned in a first direction extending from a first surface to a second surface, and an integrated concentration obtained by integrating an impurity concentration value in the first direction from (i) the first surface that is a junction interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type to (ii) a boundary between a first impurity concentration peak of the plurality of impurity concentration peaks that is the closest to the first surface and a second impurity concentration peak of the plurality of impurity concentration peaks that is the second closest to the first surface is equal to or lower than a critical integrated concentration.