IGBT p-type Floating Region Segmentation for Switching Loss Reduction

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Solution Overview

Problem

Current semiconductor devices with EGE-type active cell regions face challenges in minimizing the influence of displacement current on gate potential during switching operations, especially when inductance is connected as a load, and require improved performance to enhance the injection enhancement (IE) effect.

Innovation Solution

The semiconductor device incorporates a configuration with EGE-type active cell regions, where the p-type floating region in the inactive cell region is divided by trenches, increasing gate capacitance and reducing the discharge path for holes, thereby enhancing the IE effect and decreasing switching losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If EGE-type active cell region is used, then influence of displacement current on gate potential is reduced, but performance such as IE effect needs further improvement

Engineering Contradiction:
Improveinfluence of displacement current on gate potentialVSAvoidIE effect performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The inactive cell region is divided into multiple inactive cell sub-regions by introducing additional trenches. This segmentation increases gate capacitance and reduces the discharge path for holes, thereby enhancing the IE effect while maintaining the reduced displacement current influence on gate potential

Inventive Principle:
Principle #1Segmentation

2Productivity

If p-type floating region is divided by trenches, then gate capacitance increases and discharge path for holes is reduced, but device complexity increases

Engineering Contradiction:
Improvegate capacitance and IE effectVSAvoidtrench structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The inactive cell region is segmented into multiple sub-regions using additional trenches, which divides the p-type floating region and increases gate capacitance. This segmentation also reduces the discharge path for holes, enhancing the IE effect while managing device complexity through structured division

Inventive Principle:
Principle #1Segmentation

3Loss of energy

If additional trenches are introduced in inactive cell region, then switching losses are reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveswitching lossesVSAvoidtrench fabrication complexity
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

Additional trenches are introduced to segment the inactive cell region, which reduces switching losses by increasing gate capacitance and reducing hole discharge paths. The segmentation approach manages manufacturing complexity by creating a structured, repeatable pattern of trenches

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses rapid current changes and oscillations, improves the IE effect, and reduces switching losses during turn-on operations, leading to enhanced performance and reliability of the semiconductor device.

Implementation Method 1

The IE effect serves to increase the concentration of charges accumulated in a drift region by preventing holes from being discharged from the emitter electrode side when the IGBT is in an on state

Methodology Applied
Scientific EffectInjection enhancement effect:

Implementation Method 2

the p-type floating region in the inactive cell region is divided by trenches, increasing gate capacitance and reducing the discharge path for holes

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentEP3147950B1Semiconductor device and method of manufacturing the same
Publication Date: 2021.03.24 RENESAS ELECTRONICS CORP
  • EP3147950B1 patent drawingFigure 1
  • EP3147950B1 patent drawingFigure 2
  • EP3147950B1 patent drawingFigure 3

AI summary

A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.