IGBT Floating Regions for Turn-on Loss and Breakdown Voltage

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Solution Overview

Problem

Conventional semiconductor devices, such as IGBTs, face challenges in optimizing turn-on loss and ON voltage characteristics due to limitations in carrier injection and electric field distribution.

Innovation Solution

The semiconductor device incorporates a unique structure with a gate trench portion, mesa portions, and floating regions, where the second mesa portion has a wider width than the first mesa portion, and floating regions are strategically placed to enhance carrier injection and distribute electric fields uniformly, thereby reducing turn-on loss and optimizing ON voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional IGBT structure is used, then manufacturing process is simple, but turn-on loss cannot be effectively suppressed

Engineering Contradiction:
Improveturn-on lossVSAvoidstructure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The device is segmented into distinct functional regions: gate trench portions extending into the semiconductor substrate, first mesa portions adjacent to gate trenches, and second mesa portions with floating regions. This segmentation allows independent optimization of carrier injection (through gate trenches and accumulation regions) and electric field distribution (through floating regions in second mesa portions), effectively suppressing turn-on loss while maintaining manageable structural complexity through systematic division of functions.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If carrier injection is enhanced to reduce ON voltage, then turn-on loss decreases, but electric field distribution becomes non-uniform causing breakdown voltage degradation

Engineering Contradiction:
Improveturn-on lossVSAvoidbreakdown voltage
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

Different regions are assigned different doping concentrations and structures to optimize local functions: accumulation regions with high doping concentration adjacent to gate trenches enhance carrier injection and reduce ON voltage locally, while floating regions in second mesa portions provide localized electric field distribution. This local quality differentiation allows simultaneous optimization of turn-on characteristics and breakdown voltage reliability without compromising either parameter.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses turn-on loss and improves the tradeoff between ON voltage and turn-off loss, while preventing breakdown voltage degradation by ensuring uniform electric field distribution.

Implementation Method 1

a first conductivity type accumulation region having doping concentration higher than that in the drift region, which is provided being in direct contact with the gate trench portion above the drift region

Methodology Applied
Scientific EffectCarrier accumulation:

Implementation Method 2

electrically floating second conductivity type floating regions which are spaced from the gate trench portion below the base region

Methodology Applied
Scientific EffectElectric field distribution: Electric Field

Data Source

PatentUS10461180B2Semiconductor device
Publication Date: 2019.10.29 FUJI ELECTRIC CO LTD
  • US10461180B2 patent drawing
  • US10461180B2 patent drawing
  • US10461180B2 patent drawing

AI summary

A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.