IGBT-FWD Semiconductor Layout for Rear-Surface Avalanche Withstand
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Solution Overview
Problem
Conventional semiconductor devices with IGBT and FWD configurations face challenges in achieving high avalanche withstand capability due to rear-surface avalanche breakdown, particularly at the boundary between the transistor and diode portions, where the current density is high and the semiconductor substrate thickness is reduced, leading to electric field concentration.
Innovation Solution
The semiconductor device incorporates a lower surface region with increased hole implantation in the diode portion, positioned between the transistor and diode portions, and a buffer region with higher doping concentration to enhance the avalanche withstand capability, along with specific doping concentrations and thicknesses in the overlap and thick portions to manage electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor substrate thickness is reduced in the diode portion to improve current density, then the current density increases, but the avalanche withstand capability deteriorates due to electric field concentration at the boundary
Solution Approach 1:
The patent applies local quality by creating a lower surface region with distinct properties (higher hole concentration, increased thickness) at the boundary between transistor and diode portions. This localized modification allows the boundary area to have different characteristics from the bulk diode region, specifically enhancing avalanche withstand capability where it is most needed while maintaining high current density in the diode portion overall.
Solution Approach 2:
The patent implements preliminary action by pre-forming the lower surface region with increased hole concentration and thickness before final device operation. This preparatory structuring of the boundary area in advance ensures that when high current flows through the diode portion, the avalanche breakdown field is already distributed favorably, preventing premature breakdown and enabling sustained high current density operation.
2Reliability
If hole implantation is increased in the diode portion boundary region to improve avalanche withstand capability, then the breakdown voltage increases, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the lower surface region with existing manufacturing processes. The lower surface region is created by extending the hole implantation process that is already used for forming the collector region, rather than introducing a completely separate processing step. This integration reduces manufacturing complexity while achieving the desired breakdown voltage enhancement.
Solution Approach 2:
The patent applies parameter changes by modifying the hole implantation parameters (dose, energy, depth) in the boundary region to create the lower surface region. By carefully controlling these parameters, the patent achieves the necessary increase in hole concentration and region thickness to enhance breakdown voltage while keeping the process compatible with standard semiconductor manufacturing capabilities.
3Reliability
If the overlap region length is increased to improve electric field distribution, then the avalanche withstand capability improves, but the device area increases
Solution Approach 1:
The patent transitions from a two-dimensional planar overlap region to a three-dimensional lower surface region by extending the modified region into the substrate depth. This vertical dimensionality change allows the patent to achieve improved electric field distribution and avalanche withstand capability without proportionally increasing the horizontal device area, as the key modifications occur in the depth direction rather than the planar direction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively improves the rear-surface avalanche withstand capability by increasing hole implantation and securing the breakdown voltage, reducing the likelihood of breakdown at the boundary between the transistor and diode portions.
Implementation Method 1
Conventional semiconductor devices with IGBT and FWD configurations face challenges in achieving high avalanche withstand capability due to rear-surface avalanche breakdown
Implementation Method 2
a buffer region with higher doping concentration to enhance the avalanche withstand capability, along with specific doping concentrations and thicknesses in the overlap and thick portions to manage electric field distribution
Data Source
AI summary
Provided is a semiconductor device, comprising: a semiconductor substrate; a transistor portion including an emitter region on the top of the semiconductor substrate; a diode portion including a cathode region on the bottom of the semiconductor substrate and a second conductivity type overlap region in a region other than the cathode region and arranged alongside to the transistor portion a preset arrangement direction on the top of the semiconductor substrate; and an interlayer dielectric film provided between the semiconductor substrate and an emitter electrode and including a contact hole for connecting the emitter electrode and the diode portion. The overlap region is provided to have a first length between the end of the emitter region and the end of the cathode region and a second length, which is shorter than the first length, between the end of the contact hole and the end of the cathode region.