IGBT Gate Busbar Layout for Uniform Cell Turn-On
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Solution Overview
Problem
In power semiconductor devices, particularly IGBTs, the parasitic parameters of the gate busbar cause signal delay and uneven current distribution due to increasing chip size and frequency, leading to inconsistent gate signal reception across cells.
Innovation Solution
A semiconductor device design featuring emitter segments with non-uniform lengths and a gate busbar with varying widths or thicknesses, where the lengths and dimensions of the emitter segments and gate busbar portions change with distance from the gate pad to ensure consistent gate signal arrival across cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the chip size increases to meet high power demand, then the power handling capability improves, but the parasitic parameters of the gate busbar increase causing signal delay and uneven current distribution
Solution Approach 1:
The gate busbar is designed with non-uniform width where the width varies at different locations. Specifically, the gate busbar has a larger width near the gate pad and gradually decreases toward the peripheral cells, creating local variations in electrical properties to compensate for the increased parasitic effects in larger chips.
Solution Approach 2:
The physical parameter of the gate busbar (width) is changed along its length to optimize performance. The width parameter varies continuously or in steps from the gate pad outward, transforming the uniform structure into a tapered structure that adjusts electrical characteristics to maintain signal consistency across the larger chip area.
2Power
If more cells are connected in parallel to increase power output, then the power capability improves, but the gate signal delay increases due to longer busbar paths
Solution Approach 1:
Different sections of the gate busbar serving different cell groups have different widths. Cells closer to the gate pad receive signals through narrower busbar sections, while peripheral cells receive signals through wider busbar sections, locally adjusting the electrical characteristics to equalize signal arrival times across all cell groups.
3Reliability
If the gate busbar width is increased to reduce parasitic effects, then the signal distribution improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of using multiple separate busbars or complex three-dimensional structures, the invention achieves improved signal distribution by simply varying the width parameter of a single planar gate busbar. This maintains manufacturing simplicity while improving electrical performance through geometric parameter optimization.
Data Source
AI summary
A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.