IGBT Gate Busbar Layout for Uniform Gate Signal Timing
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Solution Overview
Problem
In power semiconductor devices, particularly IGBTs, the parasitic parameters of the gate busbar cause signal delay and uneven current distribution due to increasing chip sizes and high-frequency applications, with existing solutions only addressing the width of the annular gate busbar in the peripheral area, offering limited effectiveness.
Innovation Solution
A semiconductor device design featuring emitter segments with non-uniform lengths and a gate busbar with non-uniform widths or thicknesses to ensure consistent gate signal delivery to each cell, achieved by varying the widths or thicknesses of the gate busbar portions along specific axes to maintain signal consistency across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the chip size is increased to meet high power demands, then the power handling capability is improved, but the parasitic parameters of the gate busbar increase causing signal delay and uneven current distribution
Solution Approach 1:
The gate busbar is designed with non-uniform width or thickness, where the width or thickness varies at different positions along the busbar. Specifically, the gate busbar has a larger width or thickness near the gate pad and a smaller width or thickness farther from the gate pad, compensating for the increased parasitic parameters in larger chips and ensuring uniform current distribution across all cells.
2Productivity
If the distance from gate pad to cells is increased to accommodate more cells in parallel, then the current capacity is improved, but the gate signal delay increases causing uneven current distribution
Solution Approach 1:
The physical parameters of the gate busbar (width or thickness) are changed non-uniformly along its length. By adjusting these dimensions, the resistance and inductance of the gate busbar are compensated at different positions, ensuring that gate signals arrive at all cells simultaneously even when cells are located at different distances from the gate pad.
3Ease of manufacture
If a uniform gate busbar design is used, then the manufacturing simplicity is improved, but the current sharing among cells becomes uneven
Solution Approach 1:
Instead of a uniform gate busbar, the invention employs a gate busbar with locally varied width or thickness. This non-uniform design compensates for the different current paths and parasitic parameters that cells experience based on their distance from the gate pad, achieving uniform current sharing while remaining manufacturable through standard semiconductor fabrication processes.
Data Source
AI summary
A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.