IGBT Gate Current Slope Measurement for Miller Plateau Estimation
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Solution Overview
Problem
Conventional solutions for controlling the turn-off of Insulated Gate Bipolar Transistors (IGBTs) face challenges in preventing overvoltages and electromagnetic interferences during rapid switching, as they either degrade the turn-off time or require complex feedback control loops, and measuring collector-emitter voltage is noisy and difficult.
Innovation Solution
A gate drive circuit that uses a current measurement circuit to determine a first time increment and a proportional timer circuit to estimate the start of the Miller plateau, allowing for a controlled reduction of the gate current to prevent voltage overshoot while maintaining acceptable turn-off times, by generating an intermediate gate current level between full turn-on and turn-off voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a small external resistor is connected in series with the gate control terminal to limit discharge current and reduce overvoltages, then overvoltages across the power transistor are reduced, but the turn-off time is degraded and switching losses are increased
Solution Approach 1:
The gate control voltage is dynamically adjusted during the turn-off process. Instead of using a fixed resistor that continuously limits current, the control circuit actively modulates the gate voltage to provide high current initially for fast switching, then reduces current as the transistor approaches cutoff, optimizing both speed and voltage control throughout the transition
Solution Approach 2:
The invention changes the gate control voltage parameter over time during turn-off. The control circuit generates a time-varying gate voltage that starts at a high level to enable rapid discharge of gate capacitance, then progressively reduces to an intermediate level to control the rate of voltage rise across the transistor, thereby achieving fast turn-off without excessive overvoltages
2Object-affected harmful factors
If active voltage control is used to generate intermediate gate voltage levels to reduce overvoltages while maintaining turn-off time, then overvoltages are reduced and turn-off time is maintained, but a complex feedback control loop is required
Solution Approach 1:
The control circuit pre-calculates and generates the appropriate gate voltage waveform before the actual turn-off event occurs. By having the intermediate voltage levels ready in advance through programmed control logic, the system eliminates the need for real-time feedback adjustment during the critical switching transient, simplifying the control architecture while maintaining precise voltage control
Solution Approach 2:
The invention introduces an intermediate control stage between the digital control logic and the power transistor gate. This intermediary circuit generates the analog gate drive signals with appropriate voltage levels and timing, acting as a buffer that translates digital control commands into precise analog gate voltage waveforms without requiring direct feedback from the power transistor
3Object-affected harmful factors
If voltage across collector and emitter is measured to prevent overvoltages, then overvoltage protection is achieved, but the measurement is difficult due to noisy signal and high voltage requirements
Solution Approach 1:
Instead of directly measuring the high-voltage collector-emitter signal, the invention uses the gate control voltage as an intermediary parameter that correlates with the transistor's switching state and voltage conditions. By monitoring and controlling the gate voltage, the system indirectly manages and protects against collector-emitter overvoltages without requiring direct high-voltage signal measurement
Data Source
AI summary
A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.