IGBT Gate Polysilicon Capacitance via Local SIPOS Contact
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Solution Overview
Problem
Existing insulated gate bipolar transistors (IGBTs) face challenges in achieving high controllability due to low gate-emitter capacitance relative to Miller capacitance, which affects their switching efficiency in applications like electric vehicles and trains.
Innovation Solution
A novel IGBT design with a specific arrangement of SIPOS and insulating layers, where the SIPOS layer is in electrical contact with the gate polysilicon layer in the central area, increasing the gate-emitter capacitance by reducing the separation between the gate polysilicon and emitter metal layers through a thin second insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate polysilicon layer is completely separated from the emitter metal layer by insulating layers, then electrical isolation is improved, but gate-emitter capacitance decreases
Solution Approach 1:
The patent applies local quality by creating different electrical connection states in different regions of the gate structure. The gate polysilicon layer is selectively connected to the emitter metal layer in central regions while remaining isolated in peripheral regions, allowing simultaneous optimization of capacitance and isolation properties in different locations
Solution Approach 2:
The gate structure is segmented into central and peripheral regions with different electrical characteristics. The central region provides capacitive coupling through direct contact, while the peripheral region maintains electrical isolation, dividing the gate structure into functional zones that address both contradictory requirements
2Quantity of substance
If the gate polysilicon layer is in direct contact with the emitter metal layer, then gate-emitter capacitance increases, but electrical isolation deteriorates
Solution Approach 1:
Direct contact between gate polysilicon and emitter metal is implemented only in central regions where high capacitance is needed, while peripheral regions maintain full insulating separation. This localized approach allows capacitance enhancement without compromising overall electrical isolation
Solution Approach 2:
The insulating layers (first insulating layer and second insulating layer) act as intermediaries that selectively mediate the electrical interaction between gate polysilicon and emitter metal. In central regions, these intermediaries are absent allowing direct contact, while in peripheral regions they maintain isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly enhances the gate-emitter capacitance, improving the controllability and switching efficiency of IGBTs, allowing for more precise control of electric power in high-efficiency applications.
Implementation Method 1
each gate polysilicon layer is arranged at a surface of the semiconductor substrate in the gate regions and is separated from the semiconductor substrate by the first insulating layer
Implementation Method 2
A controllability of an IGBT can strongly depend on capacitances occurring within the IGBT such as a gate-emitter capacitance
Implementation Method 3
in the peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer by an intermediate third insulating layer
Data Source
AI summary
An IGBT is disclosed with a high emitter-gate capacitance, wherein an active cell region can include plural emitter and gate regions. A termination edge region can include a varied lateral doping region VLD. Each gate polysilicon layer can be arranged at a surface of the semiconductor substrate in the gate regions, separated from the semiconductor substrate by a first insulating layer. A first SIPOS layer and a covering second insulating layer overlie at least portions of the gate polysilicon layer. In a central area, the gate polysilicon layer is in electrical contact with the overlying first SIPOS layer whereas, in a peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer. A substrate surface at the VLD region is in electrical contact with a second SIPOS layer, and an increased gate-emitter capacitance may be achieved by slightly modifying etch masks during manufacturing.