IGBT Gate Trench Layout for Fast Gate Distribution
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Solution Overview
Problem
State-of-the-art power semiconductor devices, such as IGBTs, face challenges in reducing conduction losses in the on-state and maintaining high voltage withstand in the off-state due to the presence of busbars, which reduce the active conduction area and are not suitable for presspack devices due to non-planar top surfaces.
Innovation Solution
A gate-controlled semiconductor device with a secondary trench that reduces latency in gate voltage distribution, eliminating the need for busbars, and featuring a thick insulation layer to minimize capacitance effects, along with auxiliary trenches to prevent breakdown voltage degradation and improve switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If busbars are used to reduce latency in gate voltage distribution, then gate voltage distribution speed is improved, but active conduction area is reduced and device planarity is degraded
Solution Approach 1:
The patent transitions from planar busbar structures to three-dimensional trench structures that extend vertically into the drift region. This dimensional change allows the gate voltage distribution network to occupy the vertical dimension rather than consuming horizontal conduction area, thereby resolving the contradiction between fast voltage distribution and maximum conduction area utilization
Solution Approach 2:
The patent introduces an insulation layer as an intermediary between the gate trench and the drift region. This thick insulation layer (3000-5000 Å) serves as a mediator that provides electrical isolation while allowing the gate voltage to be distributed effectively through the trench structure without requiring traditional busbars on the surface
2Loss of time
If busbars are used to reduce latency in gate voltage distribution, then gate voltage distribution speed is improved, but device planarity is degraded making presspack devices unsuitable
Solution Approach 1:
The gate distribution network is moved from the two-dimensional surface plane to the three-dimensional subsurface volume by creating trenches that extend vertically into the drift region. This allows the distribution function to be achieved without compromising the surface planarity required for presspack device assembly
Solution Approach 2:
The gate distribution structure is extracted from the surface plane and placed into the subsurface volume through trench formation. This extraction eliminates the conflict between having a fast distribution network and maintaining a planar surface, as the distribution network now occupies a different spatial location
3Speed
If thick insulation layer is used on secondary trench to eliminate capacitance effects, then switching speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies a particular parameter range for the insulation layer thickness (3000-5000 Å, preferably 3500-4500 Å, most preferably 4000 Å) that optimizes the balance between eliminating capacitance effects for fast switching and maintaining manufacturability. This parameter optimization resolves the contradiction by identifying a specific thickness range that achieves the desired electrical performance without excessive manufacturing difficulty
Data Source
AI summary
We herein describe a gate controlled semiconductor device having a plurality of gate trenches, in which the plurality of gate trenches are laterally spaced from each other in a first dimension, current flows in a second dimension substantially transverse to the first dimension, and the plurality of gate trenches each extend in a third dimension of the device. A secondary trench extends in the first dimension of the device, and the secondary trench contacts each gate trench of the plurality of gate trenches at a plurality of intersection regions laterally spaced along the secondary trench.