IGBT Gate Wiring Stress Reduction via Multilayer Sintering
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Solution Overview
Problem
The existing joining techniques for semiconductor devices, particularly those using cupric oxide particles, face issues with thermal fatigue and excessive stress during the sintering process, leading to crack generation and defects in the gate wiring portion of semiconductor chips like IGBTs, due to differences in thermal expansion coefficients.
Innovation Solution
A semiconductor device with a multilayer structure comprising an emitter electrode and a sintered layer continuously present over the emitter electrode connecting contact and gate wiring regions, which reduces stress and crack generation by mechanically protecting the gate wiring and using materials with intermediate thermal expansion coefficients for stress buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal plate is sintered and joined onto the semiconductor chip to buffer thermal expansion stress, then thermal fatigue resistance is improved, but excessive stress is generated in the gate wiring portion during the sintering process causing crack generation
Solution Approach 1:
The invention divides the joining structure into multiple segments: a first sintered layer joining the metal plate to the emitter electrode, and a second sintered layer joining the metal plate to the collector electrode. This segmentation allows stress to be distributed across multiple joining interfaces rather than concentrated in one location, preventing crack propagation through the gate wiring while maintaining thermal expansion buffering capability.
Solution Approach 2:
The metal plate acts as an intermediary element between the semiconductor chip and external connections. It has an intermediate thermal expansion coefficient between the chip and wiring materials, serving as a stress buffer that absorbs thermal expansion differences without transmitting excessive stress to the gate wiring during sintering and operation.
2Strength
If cupric oxide particles are used as joining material for Ni or Cu electrodes, then joining strength is improved, but thermal expansion coefficient difference causes thermal fatigue at junctions
Solution Approach 1:
The invention uses a composite structure consisting of cupric oxide particles as the joining material combined with a metal plate having intermediate thermal expansion properties. The cupric oxide provides strong joining strength to Ni or Cu electrodes, while the metal plate composite structure buffers thermal expansion stresses, preventing thermal fatigue at the junctions.
3Strength
If pressurization is applied during sintering and joining process, then joining strength is improved, but crack generation occurs in the gate wiring portion
Solution Approach 1:
The joining process is segmented into multiple stages with separate sintered layers. The first sintered layer joins the metal plate to the emitter electrode, and the second sintered layer joins the metal plate to the collector electrode. This segmentation allows pressurization to be applied in a distributed manner across different joining interfaces, reducing peak stress concentration that would otherwise cause cracks in the gate wiring.
Solution Approach 2:
The metal plate is positioned beforehand as a cushioning element between the pressing mechanism and the semiconductor chip. During the sintering process, the metal plate absorbs and distributes the applied pressure, preventing excessive localized stress from reaching the gate wiring portion and causing cracks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses excessive stress during the sintering process, reducing the likelihood of cracks and characteristic defects in the semiconductor device, thereby enhancing the reliability of the wiring connection and reducing defects such as short-circuits and breakdown voltage reductions.
Implementation Method 1
there is a difference in thermal expansion coefficient between the semiconductor chip and the wiring material
Implementation Method 2
a sintered layer arranged above the emitter electrode
Data Source
AI summary
Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions.