IGBT Structure Integrating Gated PNPN Diode With MOS Process

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current IGBT manufacturing processes are complex due to the inability to integrate with MOS device processes, leading to increased complexity and inefficiency.

Innovation Solution

The development of an IGBT structure and manufacturing method that integrates with MOS device processes by incorporating a first gated PNPN diode with specific regions and spacers, allowing for the reduction of process complexity by using existing MOS device manufacturing methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the current IGBT manufacturing process is used, then the IGBT can be produced with high output current and high input impedance, but the process complexity is greatly increased due to inability to integrate with MOS device process

Engineering Contradiction:
Improveoutput current and input impedanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the IGBT manufacturing process with the MOS device manufacturing process by integrating the formation of the gated PNPN diode structure into the existing MOS process flow. The gated PNPN diode is formed using the same semiconductor substrate, doping processes, and gate structure formation steps as the MOS device, thereby combining two previously separate manufacturing processes into one unified process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a multi-functional manufacturing process that can produce both IGBT structures and MOS devices using the same process steps. The gated PNPN diode structure shares common process elements with MOS devices, including the gate electrode formation, dielectric layer deposition, and doping processes, enabling a universal manufacturing approach that reduces overall process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the current IGBT manufacturing process is used, then the IGBT can be produced with high output current and high input impedance, but the manufacturing efficiency is reduced due to increased process complexity

Engineering Contradiction:
Improveoutput current and input impedanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the IGBT manufacturing process with the MOS device manufacturing process by integrating the formation of the gated PNPN diode structure into the existing MOS process flow. The gated PNPN diode is formed using the same semiconductor substrate, doping processes, and gate structure formation steps as the MOS device, thereby combining two previously separate manufacturing processes into one unified process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by forming the gated PNPN diode structure during the MOS device fabrication process itself, rather than as a separate subsequent step. The doping regions and gate structures for the IGBT are created during the same process windows and thermal cycles used for the MOS device, eliminating the need for additional dedicated IGBT manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11316036B2Insulated gate bipolar transistor structure and manufacturing method thereof
Publication Date: 2022.04.26 POWERCHIP SEMICON MFG CORP
  • US11316036B2 patent drawing
  • US11316036B2 patent drawing
  • US11316036B2 patent drawing

AI summary

An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.