IGBT Hole Stopper Layer Density Control for Breakdown
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Solution Overview
Problem
Semiconductor devices with insulated gate bipolar transistors (IGBTs) face a challenge in reducing on-state voltage without compromising breakdown properties, as excessive increase in the area density of the hole stopper layer can lead to decreased breakdown properties and parasitic thyristor latch-up.
Innovation Solution
A semiconductor device with a first conductivity-type semiconductor substrate, channel regions, and thinning-out regions, where the hole stopper layer is strategically placed to divide the thinning-out regions into two parts, and its area density is maintained at or below 4.0×10^12 cm^-2, ensuring reduced on-state voltage without affecting breakdown properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the area density of the hole stopper layer is increased to reduce on-state voltage, then conductivity modulation is enhanced and on-state voltage is reduced, but breakdown properties deteriorate and parasitic thyristor latch-up occurs
Solution Approach 1:
The patent applies parameter changes by precisely controlling the area density of the hole stopper layer to be within a specific range (1.0×10^12 cm^-2 to 4.0×10^12 cm^-2). This quantitative parameter control optimizes the balance between conductivity modulation (for low on-state voltage) and breakdown properties, preventing parasitic thyristor latch-up while maintaining efficient device operation.
2Reliability
If the area density of the hole stopper layer is low, then breakdown properties are maintained, but on-state voltage remains high due to insufficient conductivity modulation
Solution Approach 1:
The patent establishes a minimum area density threshold of 1.0×10^12 cm^-2 for the hole stopper layer to ensure sufficient conductivity modulation in the drift layer. This parameter setting guarantees adequate hole accumulation for low on-state voltage operation while preventing the depletion layer from punching through, thus maintaining breakdown properties.
3Power
If the area density of the hole stopper layer is excessively increased, then on-state voltage is reduced, but the depletion layer cannot punch through and parasitic thyristor latch-up occurs
Solution Approach 1:
The patent sets an upper limit of 4.0×10^12 cm^-2 for the hole stopper layer area density to prevent excessive hole accumulation that would cause the PN junction to become forward-biased. This parameter control ensures the depletion layer can still punch through properly, avoiding parasitic thyristor latch-up while maintaining low on-state voltage.
Solution Approach 2:
The patent incorporates feedback mechanisms by monitoring and controlling the area density parameter within the optimal range. This feedback approach ensures that the hole stopper layer maintains the appropriate balance between hole accumulation for conductivity modulation and preventing conditions that lead to parasitic thyristor activation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases on-state voltage while maintaining stable breakdown properties by controlling the area density of the hole stopper layer, preventing punch-through and parasitic thyristor latch-up.
Implementation Method 1
holes injected from the collector layer is accumulated by the hole stopper layer. Therefore, it is possible to increase a hole concentration of the drift layer. Because conductivity modulation is enhanced in the drift layer, an on-state voltage can be reduced.
Implementation Method 2
when a positive voltage is applied to the collector layer, a depletion layer can punch through the hole stopper layer. In this case, therefore, the breakdown properties are not affected.
Data Source
AI summary
A semiconductor device has a first conductivity-type semiconductor substrate, second conductivity-type channel regions, and second conductivity-type thinning-out regions. The channel regions and the thinning-out regions are formed adjacent to a substrate surface of the semiconductor substrate. Further, a hole stopper layer is formed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region. The hole stopper layer has an area density of equal to or less than 4.0×1012 cm−2 to permit a depletion layer to punch through the hole stopper layer, thereby to restrict breakdown properties from being decreased.