IGBT Intermediate Region Impurity Control

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Solution Overview

Problem

The challenge in mass-producing IGBTs is the significant variation in characteristics due to the difficulty in accurately controlling the n-type impurity density in the intermediate region near the gate insulating film, which affects the gate threshold value, ON voltage, and capacitance.

Innovation Solution

The n-type impurity density in the intermediate region is accurately controlled by maintaining a variation in the depth of the lower end of the intermediate region between gate electrodes to be equal to or less than 110 nm, achieved through specific ion implantation techniques and mask formation methods to ensure consistent impurity distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation is performed to form an intermediate region, then the n-type impurity density can be adjusted to reduce ON voltage, but the depth of implanted ions varies in the vicinity of gate insulating film due to gate electrode shape, causing large variation in characteristics between IGBTs during mass-production

Engineering Contradiction:
Improvecharacteristic consistencyVSAvoidn-type impurity density control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarized insulating film layer before ion implantation. This planarized layer serves as a pre-prepared structure that compensates for the gate electrode shape influence during subsequent ion implantation, ensuring uniform implantation depth across different regions including areas near gate insulating films.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a planarized insulating film as an intermediary layer between the gate electrode structure and the ion implantation process. This intermediary layer absorbs and compensates for the geometric variations caused by gate electrode shapes, preventing these variations from directly affecting the ion implantation depth and resulting impurity distribution.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the n-type impurity density in the intermediate region is not accurately controlled, then the IGBT can be manufactured with simpler processes, but the gate threshold value, ON voltage, and capacitance show large variations

Engineering Contradiction:
Improven-type impurity density controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The planarized insulating film is formed in advance before ion implantation, creating a uniform base layer that simplifies the ion implantation process. This preliminary structure eliminates the need for complex real-time adjustments during implantation, maintaining process simplicity while achieving precise impurity density control.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical state and geometry parameters of the insulating film by planarizing its surface. This parameter change transforms the insulating film from a non-planar to a planar structure, creating a uniform implantation surface that enables precise control of ion implantation depth and impurity distribution without complicating the overall process.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If the depth of the lower end of the intermediate region varies significantly, then the ion implantation process is simpler, but the n-type impurity density distribution becomes inconsistent, affecting IGBT characteristics

Engineering Contradiction:
Improvedepth control of intermediate regionVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The planarized insulating film is prepared in advance to create a uniform surface for ion implantation. This preliminary action ensures that all subsequent implantation steps occur at consistent depths, eliminating the need for multiple corrective steps to achieve uniform impurity distribution, thereby maintaining process efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent addresses the depth variation problem by introducing a planarization dimension. Instead of trying to control implantation depth directly through complex angular or positional adjustments, the solution transforms the problem into a surface planarity dimension, creating a uniformly flat implantation surface that ensures consistent depth across all regions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach stabilizes the characteristics of IGBTs during mass-production by maintaining a consistent n-type impurity density, reducing variations in gate threshold values and ON voltage, thereby enhancing the reliability and performance of the devices.

Implementation Method 1

In ion implantation for forming an intermediate region, a depth of implanted ion tends to become larger in the vicinity of the gate insulating film than in other regions

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9608071B2IGBT and IGBT manufacturing method
Publication Date: 2017.03.28 DENSO CORP
  • US9608071B2 patent drawing
  • US9608071B2 patent drawing
  • US9608071B2 patent drawing

AI summary

An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body region, an n-type drift region, a p-type collector region, trenches penetrating the emitter region, the top body region, the intermediate region and the bottom body region from an upper surface of a semiconductor substrate and reaching the drift region, and gate electrodes formed in the trenches. The method includes forming the trenches on the upper surface of the semiconductor substrate, forming the insulating film in the trenches, forming an electrode layer on the semiconductor substrate and in the trenches after forming the insulating film, planarizing an upper surface of the electrode layer, and implanting n-type impurities to a depth of the intermediate region from the upper surface side of the semiconductor substrate after planarizing the upper surface of the electrode layer.